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ADS1210 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS1210
Beschreibung 24-Bit ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 30 Seiten
ADS1210 Datasheet, Funktion
® ADS1210
ADS1211
ADS1210
ADS1211
ADS1211
ADS1210
ADS1211
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
q DELTA-SIGMA A/D CONVERTER
q 23 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 20 BITS AT 1000Hz
q DIFFERENTIAL INPUTS
q PROGRAMMABLE GAIN AMPLIFIER
q FLEXIBLE SPI COMPATIBLE SSI
INTERFACE WITH 2-WIRE MODE
q PROGRAMMABLE CUT-OFF FREQUENCY
UP TO 15.6kHz
q INTERNAL/EXTERNAL REFERENCE
q ON CHIP SELF-CALIBRATION
q ADS1211 INCLUDES 4 CHANNEL MUX
APPLICATIONS
q INDUSTRIAL PROCESS CONTROL
q INSTRUMENTATION
q BLOOD ANALYSIS
q SMART TRANSMITTERS
q PORTABLE INSTRUMENTS
q WEIGH SCALES
q PRESSURE TRANSDUCERS
DESCRIPTION
The ADS1210 and ADS1211 are precision, wide
dynamic range, delta-sigma analog-to-digital converters
with 24-bit resolution operating from a single +5V
supply. The differential inputs are ideal for direct
connection to transducers or low level voltage sig-
nals. The delta-sigma architecture is used for wide
dynamic range and to guarantee 22 bits of no missing
code performance. An effective resolution of 23 bits
is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective
resolutions of 20 bits can be maintained up to a
sample rate of 1kHz through the use of the unique
Turbo modulator mode of operation. The dynamic
range of the converters is further increased by provid-
ing a low-noise programmable gain amplifier with a
gain range of 1 to 16 in binary steps.
The ADS1210 and ADS1211 are designed for high
resolution measurement applications in smart trans-
mitters, industrial process control, weigh scales, chro-
matography and portable instrumentation. Both con-
verters include a flexible synchronous serial interface
which is SPI compatible and also offers a two-wire
control mode for low cost isolation.
The ADS1210 is a single channel converter and is
offered in both 18-pin DIP and 18-lead SOIC pack-
ages. The ADS1211 includes a 4 channel input multi-
plexer and is available in 24-pin DIP, 24-lead SOIC,
and 28-lead SSOP packages.
AGND AVDD REFOUT
REFIN
VBIAS
XIN XOUT
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
MUX
AINP
AINN
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
PGA
Second-Order
∆∑
Modulator
Third-Order
Digital Filter
Micro Controller
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Modulator Control
Serial Interface
DGND
DVDD
SCLK
SDIO
SDOUT
ADS1211 Only
ADS1210/11
DSYNC
CS MODE DRDY
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS1-1284E
ADS1210Pr,int1ed2in1U1.S.A. May, 2000
®






ADS1210 Datasheet, Funktion
ADS1211E PIN CONFIGURATION
TOP VIEW
SSOP
AIN3N 1
AIN2P 2
AIN2N 3
AIN1P 4
AIN1N 5
AGND 6
VBIAS 7
NIC 8
NIC 9
CS 10
DSYNC 11
XIN 12
XOUT 13
DGND 14
ADS1211E
28 AIN3P
27 AIN4N
26 AIN4P
25 REFIN
24 REFOUT
23 AVDD
22 MODE
21 NIC
20 NIC
19 DRDY
18 SDOUT
17 SDIO
16 SCLK
15 DVDD
ADS1211E PIN DEFINITIONS
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NAME
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
NIC
NIC
CS
DSYNC
XIN
XOUT
DGND
DVDD
SCLK
SDIO
18 SDOUT
19 DRDY
20 NIC
21 NIC
22 MODE
23 AVDD
24 REFOUT
25 REFIN
26 AIN4P
27 AIN4N
28 AIN3P
DESCRIPTION
Inverting Input Channel 3.
Noninverting Input Channel 2.
Inverting Input Channel 2.
Noninverting Input Channel 1.
Inverting Input Channel 1.
Analog Ground.
Bias Voltage Output, +3.3V nominal.
Not Internally Connected.
Not Internally Connected.
Chip Select Input.
Control Input to Synchronize Serial Output Data.
System Clock Input.
System Clock Output (for Crystal or Resonator).
Digital Ground.
Digital Supply, +5V nominal.
Clock Input/Output for serial data transfer.
Serial Data Input (can also function as Serial Data
Output).
Serial Data Output.
Data Ready.
Not Internally Connected.
Not Internally Connected.
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output: +2.5V nominal.
Reference Input.
Noninverting Input Channel 4.
Inverting Input Channel 4.
Noninverting Input Channel 3.
®
ADS1210, 1211
6

6 Page









ADS1210 pdf, datenblatt
Filter Equation
The digital filter is described by the following transfer
function:
3
| H (f) | =
sin

π•fN
f MOD

N
sin
π•f
f MOD

where N is the Decimation Ratio.
This filter has a (sin(x)/x)3 response and is referred to a sinc3
filter. For the ADS1210/11, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
Filter Settling
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1211) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete set-
tling. For example, on the ADS1211, the fourth conversion
result after a channel change will be valid (see Figure 4).
Significant Analog Input Change
or
ADS1211 Channel Change
DRDY
Valid
Data
Valid
Data
Data
not
Valid
Data
not
Valid
Data
not
Valid
Valid
Data
Valid
Data
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Perfor-
mance Curves for more information.
In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in µVrms.
Data
Rate
(Hz)
10
20
40
50
60
100
1000
Turbo
Mode
Rate 1
21.5
21.0
20.0
20.0
19.5
18.0
10.0
Effective Resolution (Bits rms)
Turbo
Mode
Rate 2
Turbo
Mode
Rate 4
Turbo
Mode
Rate 8
22.0
22.0
21.5
21.5
21.0
20.0
12.5
22.5
22.0
22.0
21.5
21.5
21.0
15.0
22.5
22.5
22.0
22.0
21.5
17.5
Turbo
Mode
Rate 16
23.0
23.0
23.0
22.5
20.0
TABLE IV. Effective Resolution vs Data Rate and Turbo Mode
Rate. (Gain setting of 1 and 10MHz clock.)
DATA
RATE
(Hz)
10
20
40
50
60
100
1000
TURBO
MODE
RATE 1
2.9
4.3
6.9
8.1
10.5
26.9
6909.7
NOISE LEVEL (µVrms)
TURBO
MODE
RATE 2
TURBO
MODE
RATE 4
TURBO
MODE
RATE 8
1.7
2.1
3.0
3.2
3.9
6.9
1354.5
1.3
1.7
2.3
2.4
2.6
3.5
238.4
1.3
1.6
1.8
1.9
2.7
46.6
TURBO
MODE
RATE 16
1.0
1.0
1.0
1.4
7.8
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 10MHz clock.)
The Turbo Mode feature allows trade-offs to be made
between the ADS1210/11 XIN clock frequency, power dissi-
pation, and effective resolution. If a 5MHz clock is available
but a 10MHz clock is needed to achieve the desired perfor-
mance, a Turbo Mode Rate of 2X will result in the same
effective resolution. Table VI provides a comparison of
effective resolution at various clock frequencies, data rates,
and Turbo Mode Rates.
Serial
I/O
tDATA
FIGURE 4. Asynchronous ADS1210/11 Analog Input Volt-
age Step or ADS1211 Channel Change to Fully
Settled Output Data.
TURBO MODE
The ADS1210/11 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
DATA
RATE
(Hz)
60
60
60
60
60
100
100
100
100
100
XIN CLOCK
FREQUENCY
(MHz)
10
5
2.5
1.25
0.625
10
5
2.5
1.25
0.625
TURBO
MODE
RATE
1
2
4
8
16
1
2
4
8
16
EFFECTIVE
RESOLUTION
(Bits rms)
19.5
19.5
19.5
19.5
19.5
18.0
18.0
18.0
18.0
18.0
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain set-
ting of 1.)
®
ADS1210, 1211
12

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