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PDF AK5392 Data sheet ( Hoja de datos )
| Número de pieza | AK5392 | |
| Descripción | Enhanced Dual Bit 24Bit ADC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK5392]
AK5392
Enhanced Dual Bit ∆Σ 24Bit ADC
General Description
The AK5392 is a 24bit, 128x oversampling 2ch A/D Converterfor professional digital audio systems. The modulator
in the AK5392 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wider
dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. The
AK5392 performs 116dB dynamic range, so the device is suitable for professional studio equipments such as digital
mixer, digital VTR etc.
Features
Enhanced Dual Bit ADC
Sampling Rate: 1kHz∼54kHz
Full Differential Inputs
S/(N+D): 105dB
DR: 116dB
S/N: 116dB
High Performance Linear Phase Digital Anti-Alias filter
• Passband: 0∼21.768kHz(@fs=48kHz)
• Ripple: 0.001dB
• Stopband: 110dB
Digital HPF & Offset Calibration for Offset Cancel
Master Clock: 256/384fs
Power Supply: 5V±5%(Analog), 3∼5.25V(Digital)
Power Dissipation: 470mW
Package: 28pin SOP
0188-E-01
1997/11
-1-
1 page  
ASAHI KASEI
[AK5392]
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1 )
Parameter
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2 )
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Note: 1 . All voltages with respect to ground.
2 . AGND and BGND must be same voltage.
Symbol
VA
VD
∆GND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-
-
-0.3
-0.3
-10
-65
max
6.0
6.0
0.3
±10
VA+0.3
VD+0.3
70
150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Units
V
V
V
mA
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1 )
Parameter
Symbol
min
Power Supplies: Analog
VA 4.75
(Note 3 ) Digital
VD 3.0
Notes: 1 . All voltages with respect to ground.
3 . The power up sequence between VA and VD is not critical.
typ
5.0
3.3
max
5.25
5.25
Units
V
V
* AKM assumes no responsibility for the usage beyond the conditions in this data
sheet.
0188-E-01
1997/11
-5-
5 Page 
ASAHI KASEI
[AK5392]
OPERATION OVERVIEW
System Clock Input
The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting CMODE pin.
When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5392.
As the AK5392 includes the phase detect circuit for LRCK, the AK5392 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
256fs
384fs
SCLK(128fs)
8.1920MHz 12.2880MHz 4.0960MHz
11.2896MHz 16.9344MHz 5.6448MHz
12.2880MHz 18.4320MHz 6.1440MHz
Table 1 . Examples of System Clock
Serial Data Interface
AK5392 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 2 ). The
data format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2 SMODE1
Mode
L L Slave Mode
L H Master Mode
H L I2S Slave Mode
H H I2S Master Mode
Table 2 . Serial I/F Format
LRCK
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
0188-E-01
- 11 -
1997/11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AK5392.PDF ] | |
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