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PDF AK5352 Data sheet ( Hoja de datos )

Número de pieza AK5352
Descripción 96kHz Sampling 20bit ADC
Fabricantes Asahi Kasei Microsystems 
Logotipo Asahi Kasei Microsystems Logotipo



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No Preview Available ! AK5352 Hoja de datos, Descripción, Manual

ASAHI KASEI
[AK5352]
AK5352
96kHz Sampling ∆Σ 20bit ADC
GENERAL DESCRIPTION
The AK5352 is a 20-bit, 96kHz sampling rate for DAT and DVD, 64x oversampling rate(64fs), 2-channel A/D
converter for stereo digital systems. The ∆Σ modulator in the AK5352 uses the new developed Enhanced Dual
bit architecture. This new architecture achieves the wider dynamic range, while keeping much the same
superior distortion characteristics as the conventional Single bit way.
The AK5352 is available in a small 24pin VSOP package which will reduce your system space.
FEATURES
† Sampling Rate up to 96kHz
† Full-differential inputs
† S/(N+D): 97dB
† DR, S/N: 104dB
† Linear phase digital filter
Pass band: 0 22kHz(@fs=48kHz)
Pass band ripple: ±0.005dB
Stop band attenuation: 80dB
† Digital HPF for DC-offset cancel
† Master clock: 256fs/384fs
† Power supply: 5V±5%
† Small package: 24pinVSOP
0155-E-00
-1-
1997/1

1 page




AK5352 pdf
ASAHI KASEI
[AK5352]
ABSOLUTE MAXIMUM RATINGS
(AGND,DGND=0V; Note 1 )
Parameter
Symbol
min
max
DC Power Supply:Analog Power(VA pin)
VA -0.3
6.0
Digital Power(VD pin) (Note 2 )
VD -0.3 6.0/VB+0.3
Substrate Power(VB pin)
Input Current (Any pin except supplies)
VB -0.3
IIN -
6.0
±10
Analog Input Voltage
VINA -0.3 6.0/VA+0.3
AINL+,AINL-,AINR+,AINR-pins (Note 2 )
Digital Input Voltage
(Note 2 )
VIND -0.3 6.0/VB+0.3
Ambient Temperature
Ta -10
70
Storage Temperature
Tstg -65
150
Note 1 : All voltage with respect to ground.
Note 2 : Absolute maximum value is the highest voltage in 6.0V, VA+0.3V and VB+0.3V.
Units
V
V
mA
V
V
°C
°C
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND=0V; Note 1 )
Parameter
DC Power Supplies: Analog Power
Digital Power(VD pin)
Substrate Power(VB pin)(Note 3 )
Symbol
VA
VD
VB
min
4.75
4.75
4.75
typ
5.0
5.0
5.0
max
5.25
VB
5.25
Units
V
V
V
Note 1 : All voltages with respect to ground.
Note 3 : The VA and VB are connected together through the chip substrate and have several ohms
resistance. VA and VD must be same voltage.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
0155-E-00
-5-
1997/1

5 Page





AK5352 arduino
ASAHI KASEI
[AK5352]
OPERATION OVERVIEW
„ System clock
In slave mode, MCLK(256fs/384fs), LRCK(fs) and SCLK(64fs) are required for AK5352. Use a signal divided
from the MCLK for LRCK. In master mode, only MCLK is needed. A LRCK clock rate meets standard audio
rates (32kHz, 44.1kHz, 48kHz, 96kHz). MCLK=384fs does not correspond to 96kHz sampling. In slave mode,
the MCLK should be synchronized with LRCK but the phase is free of care.
The AK5352 includes the phase detect circuit for LRCK clock, the AK5352 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. (Please refer to the "Asynchronization -
reset.") When changing sampling frequency(fs) after power-up, AK5352 should be reset.
During the operation (PD="H") following external clocks should never be stopped : CLK in master mode and
MCLK, SCLK and LRCK in slave mode. When the clocks stop there is a possibility that the device comes into
a malfunction because of over currents in the dynamic logic. If the external clocks are not present, the AK5352
should be in the power-down mode. (PD="L")
„ Clock Circuit
fs
32.0kHz
44.1kHz
48.0kHz
96.0kHz
Master Clock (MCLK)
256fs
384fs
8.1920MHz 12.2880MHz
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
24.5760MHz
N/A
Table 1 . System Clock
SCLK(64fs)
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
CMODE MCLK
L 256fs
H 384fs
AK5352 has an internal divider as shown in the above figure. The device can interface either or an external
MCLK(256fs or 384fs) by controlling CMODE pin.
0155-E-00
- 11 -
1997/1

11 Page







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