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AFE2124E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer AFE2124E
Beschreibung Dual HDSL/SDSL ANALOG FRONT END
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 11 Seiten
AFE2124E Datasheet, Funktion
®
AFE2124
AFE2124
For most current data sheet and other product
information, visit www.burr-brown.com
Dual HDSL/SDSL ANALOG FRONT END
FEATURES
q SERIAL DIGITAL INTERFACE
q 48-LEAD SSOP PACKAGE
q E1, T1 AND SDSL OPERATION
q 64kbps TO 1168kbps OPERATION
q SCALEABLE DATA RATE
q 250mW POWER DISSIPATION PER
CHANNEL
q TWO COMPLETE HDSL ANALOG INTER-
FACES
q +5V POWER (5V or 3.3V Digital)
DESCRIPTION
Burr-Brown’s dual Analog Front End chip greatly re-
duces the size and cost of a DSL (Digital Subscriber
Line) system by providing all of the active analog
circuitry needed to connect two digital signal processors
to external compromise hybrids and line transformers.
The AFE2124 is optimized for HDSL (High bit rate
DSL) and for SDSL (symmetrical DSL) applications.
Because the transmit and receive filter responses auto-
matically change with clock frequency, the AFE2124 is
particularly suitable for multiple rate DSL systems. The
device operates over a wide range of data rates from
64kbps to 1168kbps.
Functionally, each half of this unit consists of a transmit
and a receive section. The transmit section generates
analog signals from 2-bit digital symbol data and filters
the analog signals to create 2B1Q symbols. The on-
board differential line driver provides a 13.5dBm signal
to the telephone line. The receive section filters and
digitizes the symbol data received on the telephone line.
This IC operates on a single 5V supply. The digital
circuitry in the unit can be connected to a supply from
3.3V to 5V. It is housed in a 48-lead SSOP package.
Pulse Former
Line Driver
txLINE
txLINE
tx and rx
Interface
Lines
tx and rx
Control
Registers
Decimation
Filter
1/2 of AFE2124
∆Σ
Modulator
Difference
Amplifier
rxHYB
rxHYB
Programmable
Gain Amp
rxLINE
rxLINE
Patents Pending
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-1538A
Printed in U.S.A. April, 1999






AFE2124E Datasheet, Funktion
THEORY OF OPERATION
The AFE2124 has two HDSL Analog Front End (AFE)
circuits on chip (channel A and channel B). Each AFE is
functionally equivalent to an AFE1124. Each AFE consists
of a transmit and a receive channel which interfaces to a
HDSL DSP through a six-wire serial interface—three wires
for the transmit channel and three wires for the receive
channel. It interfaces to the HDSL telephone line trans-
former and external compromise hybrid through transmit
and receive analog connections.
The transmit channel consists of a switched-capacitor pulse
forming network followed by a differential line driver. The
pulse-forming network receives 2-bit digital symbol data
and generates a filtered 2B1Q analog output waveform. The
differential line driver uses a composite output stage com-
bining class B operation (for high efficiency driving large
signals) with class AB operation (to minimize crossover
distortion).
The receive channel is designed around a fourth-order delta
sigma analog-to-digital converter. It includes a difference
amplifier designed to be used with an external compromise
hybrid for first-order analog echo cancellation. A program-
mable gain amplifier with gains of 0dB to +12dB is also
included. The delta sigma modulator, operating at a 24x
oversampling ratio, produces a 14-bit output at rates up to
584kHz (1.168Mbps).
The receive channel operates by summing the two differen-
tial inputs, one from the line (rxLINE) and the other from the
compromise hybrid (rxHYB). The connection of these two
inputs so that the hybrid signal is subtracted from the line
signal is described in the paragraph titled “Echo Cancella-
tion in the AFE.” The equivalent gain for each input in the
difference amp is one. The resulting signal then passes to a
programmable gain amplifier which can be set for gains of
0dB through +12dB. Following the PGA, the ADC converts
the signal to a 14-bit digital word.
The serial interface consists of three wires for transmit and
three wires for receive. The three-wire transmit interface is
transmit baud rate clock, transmit 48x oversampling clock
and Data Out. The three-wire receive interface is receive
baud rate clock, receive 48x oversampling clock and Data
In. The transmit and receive clocks are supplied to the
AFE2124 from the DSP and are completely independent.
DIGITAL DATA INTERFACE
Data is received by the AFE2124 from the DSP on the Data
In line. Data is transmitted from the AFE2124 to the DSP on
the Data Out line. The following paragraphs describe the
timing of these signals and data structure.
HDSL
DSP
rxbaudCLK
rx48xCLK
Data Out
txbaudCLK
tx48xCLK
Data In
1/2
AFE2124
FIGURE 1. DSP Interface.
4ns 4ns
txbaudCLK
from DSP
A
B
4ns 4ns
tx48xCLK
from DSP
48 1 2 3 4 15 16 47 48 1
Data In
from DSP
MSB
Bit 15
LSB
Bit 0
MSB
Bit 15
Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK
can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE2124 reads Data In on the rising edge
of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at
least 4ns after the rising edge of tx48xCLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is
read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.
FIGURE 2. Transmit Timing Diagram.
®
AFE2124
6

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