PDF AFE1115E Data sheet ( Hoja de datos )

Número de pieza	AFE1115E
Descripción	HDSL/MDSL ANALOG FRONT END WITH VCXO
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® AFE1115 ® AFE1115 HDSL/MDSL ANALOG FRONT END WITH VCXO FEATURES q COMPLETE HDSL ANALOG INTERFACE q E1, T1 AND MDSL OPERATION q VCXO AND VCXO CONTROL CIRCUITRY DESCRIPTION Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and a HDSL line transformer. The transmit and receive filter responses automatically change with clock fre- quency—allowing the AFE1115 to operate over a range of data rates from 196kbps to 1.168Mbps. Functionally, this unit consists of a transmit and a receive section with a VCXO (Voltage Controlled q +5V ONLY (5V or 3.3V Digital) q SCALEABLE DATA RATE q 300mW POWER DISSIPATION q 56-PIN SSOP Crystal Oscillator) control DAC and VCXO circuitry. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. Data to the VCXO and symbol data are sent to the AFE1115 via two serial interfaces; the receive data is available as a 14-bit parallel word. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a small 56-pin SSOP package. vcDATA vcSCLK vcLE VCXO DAC Pulse Former Filter Oscillator Output Buffer vcDAC VCXO Output VCXO Input VCXO Output Clock txLINE+ txLINE– PLLOUT PLLIN txDATA+ txSCLK txCLK rxSYNC rxLOOP rxGAIN rxDATA 2 14 Transmit Control Receive Control Decimation Filter Voltage Reference REFP VCM REFN Delta-Sigma Modulator rxLINE+ rxLINE– rxHYB+ rxHYB– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1997 Burr-Brown Corporation PDS-11384 AFPrEint1ed1in1U5.S.A. July, 1997 ® 1 page TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified. –20 –40 –60 –80 –100 –120 1K POWER SPECTRAL DENSITY LIMIT –38dBm/Hz for T1 –40dBm/Hz for E1 –80dB/decade T1 E1 196kHz –118dBm/Hz 292kHz for T1 –120dBm/Hz for E1 10K 100K Frequency (Hz) 1M 10M CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. B = 1.07 C = 1.00 D = 0.93 0.4T 0.4T NORMALIZED LEVEL QUATERNARY SYMBOLS +3 +1 –1 –3 A 0.01 0.0264 0.0088 –0.0088 –0.0264 B 1.07 2.8248 0.9416 –0.9416 –2.8248 C 1.0D0 ON2'.T640D0 EL0E.88T00E T–A0.8B80L0 E–2.6400 UNTILDEKNO00..90W33 N 20IF..405759T22EE00P..8012L86E44 IS––00..L8012E8644AV––20I..N4057G5922 IT IN? F –0.01 –0.0264 –0.0088 0.0088 0.0264 G –0.16 –0.4224 –0.1408 0.1408 0.4224 H –0.05 –0.1320 –0.0440 0.0440 0.1320 1.25T A = 0.01 F = –0.01 –1.2T –0.6T 0.5T E = 0.03 G = –0.16 H = –0.05 14T CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at Transformer Output. INPUT IMPEDANCE vs BIT RATE 200 A = 0.01 F = –0.01 50T 150 100 T1 = 784kbps, 45kΩ E1 = 1168kbps, 30kΩ 50 0 100 300 CURVE 3. Input Impedance of rxLINE and rxHYB. 500 700 900 Bit Rate (kbps) 1100 1300 5 AFE1115 ® 5 Page 13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL pulses. The power dissipa- tion specifications includes all power dissipated in the AFE1115, it does not include power dissipated in the exter- nal load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissi- pation in the AFE1115 under various conditions is shown in BIT RATE PER AFE1115 (Symbols/sec) 1168 (E1) 1168 (E1) 784 (T1) 784 (T1) 292 (1/4 E1) 292 (1/4 E1) DVDD (V) 3.3 5 3.3 5 3.3 5 TYPICAL POWER DISSIPATION IN THE AFE1115 (mW) 300 350 290 330 280 300 TABLE IV. Typical Power Dissipation. Table IV. LAYOUT The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, generate a VCXO clock, phase-lock to a high-speed digital clock, and convert the line input to a high-precision (14-bit) digital output. Thus, there are really four sections of the AFE1115: the digital section, the phase-locked loop, the VCXO and the analog section. DIGITAL LAYOUT The power supply for the digital section of the AFE1115 can range from 3.3V to 5V. This supply should be decoupled to digital ground with a ceramic 0.1µF capacitor placed as close as possible to digital ground (DGND, pin 16) and digital power (DVDD, pin 17). Ideally, both a digital power supply plane and a digital ground plane should run to and underneath the digital pins of the AFE1115 (pins 7 through 30). However, DVDD may be supplied by a wide printed circuit board trance. A digital ground plane underneath all digital pins is strongly recommended. The VCXO circuit needs special attention for layout. There is a portion of the external VCXO circuitry which needs to be as far away as possible from a ground or power plane or other traces. See the discussion below in the section titled VCXO Circuit and Layout. ANALOG LAYOUT The phase-locked loop is powered from AVDD (pin 50) and its ground is referenced to AGND (pin 49). Note that AVDD must be in the 4.75V to 5.25V range. This portion of the AFE1115 should be decoupled with both 10µF Tantalum capacitor and a 0.1µF ceramic capacitor. The ceramic ca- pacitor should be placed as close to the AFE1115 as pos- sible. The placement of the Tantalum capacitor is not as critical, but should be close to the pin. In each case, the capacitor should be connected between AVDD and AGND (pins 49 and 50). The capacitors should be placed in quiet analog areas rather than noisy digital areas. In most systems, it will be natural to derive AVDD for the phase-locked loop (PLL) from the AVDD supply. A 5Ω to 10Ω resistor should be used to connect PLL AVDD (pin 49) to the analog supply. This resistor in combination with the 10µF capacitor form a lowpass filter—keeping glitches on the analog supply from affecting the phase locked loop. Ideally, the phase-locked loop power supply would originate from the analog supply (via the 5Ω to 10Ω resistor) near the power connector for the printed circuit board. Likewise, the PLL ground should connect to a large PCB trace or small ground plane which returns to the power supply connector underneath the PLL AVDD supply path. The PLL “ground plane” should also extend underneath PLLIN and PLLOUT (pins 51 and 52). The remaining portion of the AFE1115 should be considered analog. The four non-PLL AGND pins (pins 36, 37, 42, and 46) should be connected directly to a common analog ground plane and all non-PLL AVDD pins should be con- nected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1115 by a small trace. VCXO CIRCUIT AND LAYOUT The VCXO circuitry is shown in Figure 7. The basic VCXO circuit consists of on-chip control DAC, amplifiers, Schmidt triggers, and clock buffer along with an external crystal and varactor diodes. The control DAC output (vcDAC) varies the capacitance of the varactor diodes (D1 and D2), which controls the frequency at which the crystal circuit oscillates. The buffered clock output is available at pin 3, VCXO Clock Output. Important Note: To achieve specified analog performance when using VCXO, the crystal frequency of the VCXO must be 48x the baud rate. In addition, the txCLK and the rxSYNC control signals must be derived from the VCXO clock so that the edges of the control signal are synchronized with the 48x crystal frequency. If these recommendations are followed, the key internal analog decisions are made at the time of minimum noise. As an example, for an E1 rate of 1168kbps, the symbol rate is 584k symbols per second. In this case the VCXO crystal frequency should be 48 x 584k = 28.032MHz. Likewise, for T1, the crystal frequency should be 18.816MHz. ® 11 AFE1115 11 Page

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