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ADV7191 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7191
Beschreibung Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7191 Datasheet, Funktion
a Video Encoders with Six 10-Bit DACs and
54 MHz Oversampling
ADV7190/ADV7191
FEATURES
Six High Quality 10-Bit Video DACs
Multistandard Video Input
Multistandard Video Output
4؋ Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:
Digital Noise Reduction
Gamma Correction
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Subalias Filter)
Average Brightness Detection
Field Counter
Macrovision Rev 7.1 (ADV7190 Only)
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface
Supply Voltage 5 V and 3.3 V Operation
64-Lead LQFP Package
APPLICATIONS
DVD Playback Systems,
PC Video/Multimedia Playback Systems
GENERAL DESCRIPTION
The ADV7190/ADV7191 is part of the new generation of video
encoders from Analog Devices. The device builds on the perfor-
mance of previous video encoders and provides new features such
as Digital Noise Reduction, Gamma Correction, 4¥ Oversam-
pling and 54 MHz operation, Average Brightness Detection,
Chroma Delay, an additional Chroma Filter, and so on.
The ADV7190/ADV7191 supports NTSC-M, NTSC-N (Japan),
PAL N, PAL M, PAL-B/D/G/H/I, and PAL-60 standards. Input
standards supported include ITU-R.BT656/601 4:2:2 YCrCb
in 8- or 16-bit format.
The ADV7190/ADV7191 can output Composite Video (CVBS),
S-Video (Y/C), Component YUV1, or RGB. The analog
component output is also compatible with Betacam, MII and
SMPTE/EBU N10 levels, SMPTE 170M NTSC, and ITU-
R.BT 470 PAL.
For more information about the ADV7190/ADV7191’s features,
refer to Detailed Description.
Continued on page 11
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DIGITAL
INPUT
27MHz
CLOCK
ITU–R.BT
656/601
8-BIT YCrCb
IN 4:2:2 FORMAT
VIDEO
INPUT
PROCESSING
VIDEO
SIGNAL
PROCESSING
VIDEO
OUTPUT
PROCESSING
PLL
AND
54MHz
DEMUX
AND
YCrCb–
TO–
YUV
MATRIX
COLOR CONTROL
DNR
GAMMA
CORRECTION
VBI
TELETEXT
CLOSED CAPTION
CGMS/WSS
MACROVISION
CHROMA
LPF
SSAF
LPF
LUMA
LPF
2؋
OVERSAMPLING
OR
4؋
OVERSAMPLING
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
I2C INTERFACE
ADV7190/ADV7191
ANALOG
OUTPUT
COMPOSITE VIDEO
Y [S-VIDEO]
C [S-VIDEO]
RGB
YUV
TVSCREEN
1Throughout the document, YUV refers to digital or analog component video.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest available Macrovision version.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices Inc.
I2C is a registered trademark of Philips Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADV7191 Datasheet, Funktion
ADV7190/ADV7191
5 V TIMING CHARACTERISTICS (VAA = 5 V ؎ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications
TMIN to TMAX1, unless otherwise noted.)
Parameter
Min Typ Max Unit
Test Conditions
MPU PORT2
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS2
Analog Output Delay
DAC Analog Output Skew
0 400 kHz
0.6 ms
1.3 ms
0.6 ms
0.6 ms
100 ns
300 ns
300 ns
0.6 ms
8 ns
0.1 ns
After This Period, the First Clock is Generated
Relevant for Repeated Start Condition
CLOCK CONTROL AND PIXEL PORT3
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15 (2¥ Oversampling)
Pipeline Delay, t15 (4¥ Oversampling)
TELETEXT PORT4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL
RESET Low Time
8
8
6
5
6
4
27
13
12
57
67
11
3
6
3 20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
ns
ns
ns
ns
PLL2
PLL Output Frequency
54 MHz
NOTES
1Temperature range TMIN to TMAX: 0C to 70C.
2Guaranteed by characterization.
3Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC, BLANK,
Clock: CLKIN Input.
4Teletext Port consists of:
Digital Output: TTXREQ,
Data: TTX.
Specifications subject to change without notice.
–6– REV. B

6 Page









ADV7191 pdf, datenblatt
ADV7190/ADV7191
Programmable gamma correction is also available. Figure 6 shows
the response of different gamma values to a ramp signal.
300
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
250
SIGNAL OUTPUTS
200
0.3
0.5
150
100
SIGNAL
INPUT
1.5
1.8
50
0
0 50 100 150 200 250
LOCATION
Figure 6. Signal Input (Ramp) and Selectable Gamma
Output Curves
The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the lumi-
nance signal.
The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4ϫ oversampling is
enabled. Also, the output filter requirements in 4ϫ oversampling
and 2ϫ oversampling differ, as can be seen in Figure 7.
2؋ FILTER
0dB REQUIREMENTS
4؋ FILTER
REQUIREMENTS
–30dB
6.75MHz 13.5MHz
27.0MHz
40.5MHz
54.0MHz
Figure 7. Output Filter Requirements in 4¥ Oversampling
Mode
MPEG2
PIXEL BUS
27MHz
ADV7190/ADV7191
2
؋
ENCODER
CORE
54MHz
PLL
I
N
T
E
R
P
O
L
A
T
I
O
N
6
D
A
C
O
U
T
P
U
T
S
54MHz
OUTPUT
RATE
Figure 8. PLL and 4¥ Oversampling Block Diagram
The ADV7190/ADV7191 also supports both PAL and NTSC
square pixel operation. In this case the encoder requires a
24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.
The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.
HSO/CSO and VSO TTL outputs are also available and are timed
to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7190/ADV7191 also incorporates WSS and CGMS-A
data control generation. The ADV7190 incorporates Macrovision
Rev 7.1.
The ADV7190/ADV7191 modes are set up over a 2-wire
serial bidirectional port (I2C-compatible) with two slave
addresses, and the device is register-compatible with the
ADV7172/ADV7173.
The ADV7190ADV7191 is packaged in a 64-lead LQFP
package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel
Port at a 27 MHz data rate. The pixel data is demultiplexed to
form three data paths. Y typically has a range of 16 to 235, Cr
and Cb typically have a range of 128+/–112; however, it is
possible to input data from 1 to 254 on both Y, Cb, and Cr.
The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N) and
NTSC M, N (with and without Pedestal) PAL.M (ADV7190
only) and PAL60 standards. Digital Noise Reduction can be
applied to the Y signal. Programmable gamma correction can also
be applied to the Y signal if required.
The Y data can be manipulated for contrast control and a set-up
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.
The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, (ADV7190 only) Closed-
Captioning, and Teletext levels are also added to Y and the
resultant data is interpolated to 54 MHz when 4¥ Oversampling
is enabled. The interpolated data is filtered and scaled by three
digital FIR filters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance Signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz). The
–12–
REV. B

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