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ADV7189 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7189
Beschreibung Multiformat SDTV Video Decoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7189 Datasheet, Funktion
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, Noise Shaped Video®, 12-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive-Digital-Line-Length-Tracking (ADLLT™)
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and Betacam)
12 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit/10-bit/16-bit/20-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
GENERAL DESCRIPTION
The ADV7189 integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data-compatible with 20-/16-/10-/
8-bit CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The 12-bit accurate A/D conversion provides unmatched
professional quality video performance. This allows true 10-bit
resolution in the 10-bit output mode.
The 12 analog input channels accept standard Composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Multiformat SDTV Video Decoder
ADV7189
Differential gain: 0.4% typ
Differential phase: 0.4° typ
Programmable video controls:
Peak-white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free run mode (generates stable video ouput with no I/P)
VBI decode support for
Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
80-lead LQFP Pb-free package
APPLICATIONS
High end DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Professional video products
AVR receivers
input video signal peak-to-peak range of 0.5 V to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allow very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7189 modes
are set up over a 2-wire, serial, bidirectional port (I2C-
compatible).
The ADV7189 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7189 is packaged in a small 80-lead LQFP Pb-free
package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.






ADV7189 Datasheet, Funktion
ADV7189
SPECIFICATIONS
Temperature range: TMIN to TMAX, –20°C to +70°C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless
otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS3
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Power-Up Time
Symbol
N
INL
DNL
VIH
VIL
IIN
CIN
VOH
VOL
ILEAK
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
IPWRDN
tPWRUP
Test Conditions
BSL at 54 MHz
BSL at 54 MHz
Pins listed in Note 1
All other pins
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pins listed in Note 2
All other pins
CVBS input4
YPrPb input5
Min Typ
–1.5/+2.5
–0.7/+0.7
2
–50
–10
2.4
1.65 1.8
3.0 3.3
1.65 1.8
3.15 3.3
82
2
10.5
85
180
1.5
20
Max
12
±8
–0.95/+2
0.8
+50
+10
10
0.4
50
10
20
2
3.6
2.0
3.45
Unit
Bits
LSB
LSB
V
V
µA
µA
pF
V
V
µA
µA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
1 Pins 36 and 79.
2 Pins 1, 2, 5, 6, 7, 8, 12, 17, 18, 19, 20, 21, 22, 23, 24, 32, 33, 34, 35, 73, 74, 75, 76, and 80.
3 Guaranteed by characterization.
4 ADC1 powered on.
5 All three ADCs powered on.
Rev. B | Page 6 of 104

6 Page









ADV7189 pdf, datenblatt
ADV7189
Pin No.
27
26
29
28
36
79
37
12
51
52
48, 49
54, 55
Mnemonic
LLC1
LLC2
XTAL
XTAL1
PWRDN
OE
ELPF
SFL
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
Type
O
O
I
O
I
I
I
O
O
O
I
I
Function
This is a line-locked output clock for the pixel data output by the ADV7189. Nominally 27
MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7189. Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V
27 MHz clock oscillator source is used to clock the ADV7189. In crystal mode, the crystal must
be a fundamental crystal.
A logic low on this pin places the ADV7189 in a power-down mode. Refer to the I2C Control
Register Map section for more options on power-down modes for the ADV7189.
When set to a logic low, OE enables the pixel output bus, P19–P0 of the ADV7189. A logic
high on the OE pin places Pins P19–P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 43.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
Internal Voltage Reference Output. Refer to Figure 43 for a recommended capacitor network
for this pin.
Common-Mode Level for the Internal ADCs. Refer to Figure 43 for a recommended capacitor
network for this pin.
ADC’s Capacitor Network. Refer to Figure 43 for a recommended capacitor network for this
pin.
ADC’s Capacitor Network. Refer to Figure 43 for a recommended capacitor network for this
pin.
Rev. B | Page 12 of 104

12 Page





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