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PDF Am29F017B-150EEB Data sheet ( Hoja de datos )
| Número de pieza | Am29F017B-150EEB | |
| Descripción | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only/ Uniform Sector Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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PRELIMINARY
Am29F017B
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Optimized for memory card applications
— Backwards-compatible with the Am29F016C
s 5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
s Manufactured on 0.35 µm process technology
s High performance
— Access times as fast as 70 ns
s Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
s Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
s Minimum 1,000,000 program/erase cycles per
sector guaranteed
s Package options
— 48-pin TSOP
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
s Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
s Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
s Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
Publication# 21195 Rev: B Amendment/+2
Issue Date: April 1998
1 page  
PRELIMINARY
PIN CONFIGURATION
A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE#
WE#
OE#
= Chip Enable
= Write Enable
= Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
21
A0–A20
CE#
OE#
WE#
RESET#
DQ0–DQ7
RY/BY#
8
21195B-4
Am29F017B
5
5 Page 
PRELIMINARY
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector Group
Unprotect
Completed (Note 2)
Notes:
21195B-5
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F017B
11
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet Am29F017B-150EEB.PDF ] | |
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