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Teilenummer | EM78862K |
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Beschreibung | 8-Bit RISC Type Microprocessor | |
Hersteller | ELAN Microelectronics | |
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Gesamt 30 Seiten EM78862K
8-Bit RISC Type
Microprocessor
Product
Specification
DOC VERSION 1.1
ELAN MICROELECTRONICS CORP.
July 2012
Contents
vi • Product Specification (V1.1) 07.16.2012
6 Page EM78862K
8-Bit RISC Type Microcontroller
6 Function Descriptions
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer.
Any instruction using R0 as register actually accesses the data pointed by the RAM
Select Register (R4).
6.1.2 R1 (TCC)
Increased by an external signal (16.384KHz or RC/2), or by the instruction cycle
clock.
Written and read by the program as any other register.
6.1.3 R2 (Program Counter)
The structure is depicted in Figure 6-1a below.
Generates 16K × 13 on-chip ROM addresses to the relative programming
instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC and PC+1, and then pushes it into
the STACK (14 bits).
"RET'' ("RETL k,” "RETI") instruction loads the contents of the top most Stack into
program counter.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the
9th and 10th bits are cleared to "0.''
"ADD R2, A" allows a relative address be added to the current PC, and contents of
the 9th and 10th bits are cleared to "0.''
"TBL" allows a relative address to be added into the current PC, and its 9th and 10th
bits content do not change. The most significant bit (A10~A13) will be loaded into
the status register (R5) with the contents of bits PS0~PS3 upon execution of a
"JMP,'' "CALL," “MOV R2, A,'' "ADD R2, A,'' or ”TBL” instruction.
Figure 6-1a Program Counter Organization
6 • Product Specification (V1.1) 76.16.2012
(This specification is subject to change without further notice)
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EM78862K Schematic.PDF ] |
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