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PDF EM78P808 Data sheet ( Hoja de datos )

Número de pieza EM78P808
Descripción 8-BIT OTP MICRO-CONTROLLER
Fabricantes ELAN Microelectronics 
Logotipo ELAN Microelectronics Logotipo



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No Preview Available ! EM78P808 Hoja de datos, Descripción, Manual

EM78P808
8-BIT OTP MICRO-CONTROLLER
Version 3.3
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan
TEL: (03) 5639977
FAX: (03) 5630118

1 page




EM78P808 pdf
EM78P808
8-bit OTP Micro-controller
Compatible with Bellcore GR-30-CORE (formerly as TR-NWT-000030)
Compatible with British Telecom (BT) SIN227 & SIN242
FSK demodulator for Bell 202 and ITU-T V.23 (formerly as CCITT V.23)
CALL WAITING
Operation Voltage 2.6V 5.5V
Compatible with Bellcore special report SR-TSV-002476
Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector
Good talkdown and talkoff performance
Sensitivity compensated by adjusting input OP gain
LCD (8x80, 9x80, 16x80, 24x72)
Maximum common driver pins : 16/24
Maximum segment driver pins : 80(SEG0..SEG79)/72(SEG8..SEG79)
Shared COM16 ~ COM23 pins with SEG0 ~ SEG7 pins
1/4 bias for 8, 9 and 16 common mode and 1/5 bias for 24 common mode
1/8, 1/9, 1/16, 1/24 duty
16 Level LCD contrast control (software)
Internal resistor circuit for LCD bias
Internal voltage follower for better display
Package type
136 pin Chip : EM78P808AH
128 pin QFP : (EM78P808AAQ , POVD disable) (EM78P808ABQ , POVD enable)
128 pin QFP : (EM78P808BAQ , POVD disable) (EM78P808BBQ , POVD enable)
III.Application
1. adjunct units
2. answering machines
3. feature phones
_____________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
5
1/1/2005 (V3.3)

5 Page





EM78P808 arduino
EM78P808
8-bit OTP Micro-controller
RING
TONE
KTONE
CW
CWGS
CWIN
DTMF
receiver
EST
STGT
I
O
O (PORT67)
O
I
O
I/O
OP
OP- I (PORT55)
OP+ I (PORT56)
OPO
SERIAL IO
SCK
O (PORT57)
IO (PORT60)
SDO
O (PORT61)
SDI
Comparator
CMP1
CMP2
CMP3
CURRENT DA
DAOUT
I (PORT62)
I (PORT63)
I (PORT64)
I (PORT65)
O (PORT66)
IO
P55 ~P57
P60 ~P67
P70 ~ P77
I/O
I/O
I/O
P80 ~ P87
P90 ~ P97
PB0 ~ PB7
I/O
I/O
I/O
Should be connected with RING side of twisted pair lines for
FSK.
Dual tone output pin
Key tone output. Shared with PORT67.
Gain adjustment of single-ended input OP Amp
Single-ended input OP Amp for call waiting decoder
Early steering output. Presents a logic high immediately when the
digital algorithm detects a recognizable tone-pair (signal
condition). Any momentary loss of signal condition will cause
EST to return to a logic low. This pin shared with PORT56.
Steering input/guard time output (bi-directional). A voltage
greater than Vtst detected at ST causes the device to register the
detected tone-pair and update the output latch.
A voltage less than Vtst frees the device to accept a new tone-pair.
The GT output acts to reset the external steering time-constant; its
state is a function of EST and the voltage on ST . This pin shared
with PORT55.
The negative Vin input pin of the OP. This pin shared with
PORT55.
The positive Vin input pin of the OP. This pin shared with
PORT56.
The output of OP. This pin shared with PORT57.
Master: output pin, Slave: input pin. This pin shared with
PORT60.
Output pin for serial data transferring. This pin shared with
PORT61.
Input pin for receiving data. This pin shared with PORT62.
Comparator input pins. Shared with PORT63, PORT64 and
PORT65.
Current DA output pin. It can be a control signal for sound
generating.
Shared with PORT66.
PORT 5 can be INPUT or OUTPUT port each bit.
PORT 6 can be INPUT or OUTPUT port each bit.
Internal pull high.
PORT 7 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
Auto key scan function.
Interrupt function.
PORT 8 can be INPUT or OUTPUT port each bit.
Shared with LCD Segment signal.
PORT 9 can be INPUT or OUTPUT port each bit.
Shared with LCD Segment signal.
PORT B can be INPUT or OUTPUT port each bit.
_____________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
11
1/1/2005 (V3.3)

11 Page







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