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W78C374 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W78C374
Beschreibung MONITOR CONTROLLER
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W78C374 Datasheet, Funktion
Preliminary W78E378/W78C378/W78C374
MONITOR CONTROLLER
GENERAL DESCRIPTION
The W78E378, W78C378 and W78C374B are ASIC which is a stand-alone high-performance
microcontroller specially designed for monitor control applications. The device integrates the
embedded 80C31 microcontroller core, on-chip MTP or Mask ROM, 576 bytes of RAM, and a number
of dedicated hardware monitor functions. Additional special function registers are incorporated to
control the on-chip peripheral hardware. The chip is used to control the interface signal of other
devices in the monitor and to process the video sync signals. Because of the highly integration and
Flash cell for program memory, the device can offer users the competitive advantages of low cost
and reduced development time.
FEATURES
80C31 MCU Core Embedded
32K Bytes MTP-ROM (W78E378)
32K Bytes Mask-ROM (W78C378)
16K Bytes Mask-ROM (W78C374B)
Total 576 Bytes of On-chip Data RAM
256 bytes accessed as in the 80C32
320 bytes accessed as external data memory via "MOVX @Ri"
PWM DACs
Eight 8-bit Static PWM DACs: DAC0DAC8
Three 8-bit Dynamic PWM DACs: DAC9DAC10
Sync Processor
Horizontal & Vertical Polarity Detector
Sync Separator for Composite Sync
12-bit Horizontal & Vertical Frequency Counter
Programmable Dummy Frequency Generator
Programmable H-clamp Pulse Output
SOA Interrupt
Hsync/2 Output
Serial Ports:
DDC1 Port- support DDC1
SIO1 & SIO2 Ports - each can support DDC2B/2B+/2Bi/2AB (each has 2 slave addresses)
Two 16-bit Timer/Counters (8031's Timer0 & Timer1)
One External Interrupt Input (8031's INT0 )
One Parabola Interrupt Generator
One ADC with 7 Multiplexed Analog Inputs
Two 12 mA(min) Output Pins for Driving LEDs
Watchdog Timer (222/Fosc = 0.42s @Fosc = 10 MHz)
Power Low Reset
Frequency: 10 MHz max. (with the same performance as a normal 8051 that uses 20 MHz)
Packaged in 40/32-pin 600 mil DIP & 44-pin PLCC
Publication Release Date: December 1999
- 1 - Revision A1






W78C374 Datasheet, Funktion
Preliminary W78E378/W78C378/W78C374
BLOCK DIAGRAM
VDD VSS
OSCIN
OSCOUT
RESET
80C31 Core excluding internal RAM
Note:
freq1 = freq2
freq2
freq1
Osc.
Circuit
CPU
Interrupt
Processor
Reset
Circuit
Timer 0
Timer 1
INT0 (P3.2)
T0 (P3.5)
T1 (P3.6)
Power Low
Detection
I/O Port
VPP (P3.2)
HIN, VIN
HFI (P4.0)
VOUT (P3.4)
HOUT (P3.3)
Hclamp (P2.3)
HFO (P4.7)
ADC0 (P2.4)
ADC1 (P2.5)
ADC2 (P2.6)
ADC3 (P2.7)
ADC4 (P3.5)
ADC5 (P3.6)
ADC6 (P3.7)
Watch Dog
Timer
Program Memory
Data Memory
RAM: 576 Bytes
Sync.
Processor
SIO1
SIO2
Static DACs
ADC
Dynamic DACs
8-bit Internal Bus
P1, P2, P3
P4
Note:
P1, P4.4~P4.5
P3.0~P3.1 & P3.5~P3.7
are open-drain.
SCL (P3.1)
SDA (P3.0)
SCL2 (P4.4)
SDA2 (P4.5)
DAC0~7 (P1.0~P1.7)
DAC8~10 (P2.0~P2.2)
-6-

6 Page









W78C374 pdf, datenblatt
Preliminary W78E378/W78C378/W78C374
*HFCOUNTH: Horizontal frequency counter register, high byte (Read Only)
BIT NAME
FUNCTION
0 HF8 H frequency count bit 8
1 HF9 H frequency count bit 9
2
HF10
H frequency count bit 10
3
HF11
H frequency count bit 11
45 - -
6
NOH
Set by hardware if no Hin signal
7 HPOL Hin polarity. 0: Positive, 1: Negative
*VFCOUNTL: Vertical frequency counter register, low byte (Read Only)
BIT NAME
FUNCTION
0 VF0 V frequency count bit 0
1 VF1 V frequency count bit 1
2 VF2 V frequency count bit 2
3 VF3 V frequency count bit 3
4 VF4 V frequency count bit 4
5 VF5 V frequency count bit 5
6 VF6 V frequency count bit 6
7 VF7 V frequency count bit 7
*VFCOUNTH: Vertical frequency counter register, high byte (Read Only)
BIT NAME
FUNCTION
0 VF8 V frequency count bit 8
1 VF9 V frequency count bit 9
2
VF10
V frequency count bit 10
3
VF11
V frequency count bit 11
45 - -
6
NOV
Set by hardware if no VIN signal
7 VPOL VIN polarity. 0: Positive, 1: Negative
* INTVECT: Interrupt Vector Register (Read Only)
BIT NAME
FUNCTION
0 SCLINT SCL pin pulled low detected
1 ADCINT ADC conversion completed
2 DDC1INT DDC1 port buffer empty
3 SOAINT SOA condition happen
4 VEVENT Vsync pulse detected or NOV = 1 (V counter overflow)
(The VEVENT is designed to be generated only 'one' time
if no Vsync input.)
5 PARAINT Parabola Interrupt generated
- 12 -

12 Page





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