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A3P125 Schematic ( PDF Datasheet ) - Microsemi

Teilenummer A3P125
Beschreibung ProASIC3 Flash Family FPGAs
Hersteller Microsemi
Logo Microsemi Logo 




Gesamt 30 Seiten
A3P125 Datasheet, Funktion
Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM®-enabled ProASIC®3 devices)
via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended
2.5 V / 1.8 V /
I/O
1.5 V,
Standards:
3.3 V PCI /
3L.V3TVTLP, CI-LXVCManOdSLVC3.M3 OVS/
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rateand Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor
Available with or without Debug
ProASIC3 Devices
Cortex-M1 Devices 2
A3P0151 A3P030
A3P060 A3P125 A3P250
A3P400
A3P600
A3P1000
M1A3P250 M1A3P400 M1A3P600 M1A3P1000
System Gates
15,000
30,000
60,000 125,000 250,000
400,000
600,000
1,000,000
Typical Equivalent Macrocells 128
256
512 1,024
2,048
VersaTiles (D-flip-flops)
384
768
1,536 3,072
6,144
9,216
13,824
24,576
RAM Kbits (1,024 bits)
18 36
36
54 108 144
4,608-Bit Blocks
48
8
12 24
32
FlashROM Kbits
Secure (AES) ISP 3
11
11
1
1
1
1
Yes Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
11
1
1
1
1
VersaNet Globals 4
6
6
18 18
18
18
18
18
I/O Banks
22
22
4
4
4
4
Maximum User I/Os
49
81
96 133
157
194
235
300
Package Pins
QFN
CS
VQFP
TQFP
PQFP
FBGA
QN68
QN48, QN68,
QN132
VQ100
QN132
CS121
VQ100
TQ144
FG144
QN132 QN132 5
VQ100
TQ144
PQ208
FG144
VQ100
PQ208
FG144/256
5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
† A3P015 and A3P030 devices do not support this feature.
January 2013
© 2013 Microsemi Corporation
‡ Supported only by A3P015 and A3P030 devices.
I






A3P125 Datasheet, Funktion

6 Page









A3P125 pdf, datenblatt
ProASIC3 Device Family Overview
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis (for PLL only)
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
• Output duty cycle = 50% ± 1.5% or better (for PLL only)
• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
• Maximum acquisition time = 300 µs (for PLL only)
• Low power consumption of 5 mW
• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC) (for PLL only)
Global Clocking
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
1-6 Revision 13

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