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ADAQ7980 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAQ7980
Beschreibung Integrated Data Acquisition Subsystem
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADAQ7980 Datasheet, Funktion
Data Sheet
FEATURES
Easy to use
Integrated data acquisition subsystem
All active components designed by Analog Devices, Inc.
On-board ADC driver and reference buffer
50% PCB area savings
Includes critical passive components
SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface
Daisy-chain multiple ADAQ7980/ADAQ7988 devices
Versatile supply configuration with 1.8 V/2.5 V/3 V/5 V
logic interface
Pseudo differential ADC input structure
High performance
16-bit resolution with no missing codes
Throughput: 1 MSPS (ADAQ7980) and 500 kSPS (ADAQ7988)
INL: ±8 ppm typical and 20 ppm maximum
SNR: 91.5 dB typical at 10 kHz (unity gain)
THD: −105 dB at 10 kHz
Low input bias current: 470 nA typical
Low power dissipation
21 mW typical at 1 MSPS (ADAQ7980)
16.5 mW typical at 500 kSPS (ADAQ7988)
Flexible power-down modes
Dynamic power scaling
Small, 24-lead, 5 mm × 4 mm LGA package
Wide operating temperature range: −55°C to +125°C
APPLICATIONS
Automated test equipment (ATE)
Battery powered instrumentation
Communications
Data acquisition
Process control
Medical instruments
GENERAL DESCRIPTION
The ADAQ7980/ADAQ7988 are 16-bit analog-to-digital converter
(ADC) subsystems that integrate four common signal processing
and conditioning blocks into a system in package (SiP) design
that supports a variety of applications. These devices contain
the most critical passive components, eliminating many of the
design challenges associated with traditional signal chains that
use successive approximation register (SAR) ADCs. These passive
components are crucial to achieving the specified device
performance.
16-Bit, 1 MSPS, Integrated Data
Acquisition Subsystem
ADAQ7980/ADAQ7988
FUNCTIONAL BLOCK DIAGRAM
V+ REF REF_OUT LDO_OUT VDD
PD_REF
10µF
LDO
2.2µF
PD_LDO
IN+
IN–
AMP_OUT
20
1.8nF
ADC
ADAQ7980/
ADAQ7988
VIO
SDI
SCK
SDO
CNV
V– PD_AMP ADCN GND
Figure 1.
The ADAQ7980/ADAQ7988 contain a high accuracy, low power,
16-bit SAR ADC, a low power, high bandwidth, high input
impedance ADC driver, a low power, stable reference buffer,
and an efficient power management block. Housed within a tiny,
5 mm × 4 mm LGA package, these systems simplify the design
process for data acquisition systems. The level of system integration
of the ADAQ7980/ADAQ7988 solves many design challenges,
while the devices still provide the flexibility of a configurable
ADC driver feedback loop to allow gain and/or common-mode
adjustments. A set of four device supplies provides optimal system
performance; however, single-supply operation is possible with
minimal impact on device operating specifications.
Using the SDI input, the serial peripheral interface (SPI)-
compatible serial interface features the ability to daisy-chain
multiple devices on a single, 3-wire bus and provides an optional
busy indicator. The user interface is compatible with 1.8 V, 2.5 V,
3 V, or 5 V logic.
Specified operation of these devices is from −55°C to +125°C.
Table 1. Integrated SAR ADC Subsystems
Type
500 kSPS
1000 kSPS
16-Bit
ADAQ7988
ADAQ7980
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADAQ7980 Datasheet, Funktion
ADAQ7980/ADAQ7988
Data Sheet
Parameter
ADAQ7980 Power Dissipation
V+/V−/VDD
VIO
Total
ADAQ7988 Current Draw
VIO
V+/V−
VDD
ADAQ7988 Power Dissipation
V+/V−/VDD
VIO
Total
TEMPERATURE RANGE
Specified Performance
Test Conditions/Comments
1 MSPS
1 kSPS, dynamic power scaling enabled3
500 kSPS
1 kSPS, dynamic power scaling enabled3
TMIN to TMAX
1 With all digital inputs forced to VIO or GND as required.
2 During the acquisition phase.
3 Dynamic power scaling duty cycle is 10%.
4 Calculated with the maximum supply differential and not the typical supply values.
Min
−55
Typ Max
20 36
5.8 9
1.0 1.9
21 37.94
0.15 0.17
1.35 1.85
0.73 0.8
16 26.5
5.8 9
0.5 0.95
16.5 27.54
+125
Unit
mW
mW
mW
mW
mA
mA
mA
mW
mW
mW
mW
°C
Rev. 0 | Page 6 of 49

6 Page









ADAQ7980 pdf, datenblatt
ADAQ7980/ADAQ7988
Data Sheet
Parameter
Falling Edge to Data Remains Valid
Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3.0 V
VIO Above 1.7 V
SDI VALID SETUP TIME From CNV RISING EDGE
Symbol
tHSDO
tDSDO
tSSDICNV
Min
3
5
Typ Max
9.5
11
21
1 The acquisition phase is the time available for the ADC sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1 MSPS.
Unit
ns
ns
ns
ns
ns
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3 OR TABLE 5.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 12 of 49

12 Page





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