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33937A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 33937A
Beschreibung Three phase field effect transistor pre-driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
33937A Datasheet, Funktion
NXP Semiconductors
Technical Data
Three phase field effect transistor
pre-driver
Document Number: MC33937
Rev. 9.0, 7/2016
33937A
The 33937A is a field effect transistor (FET) pre-drivers designed for three
phase motor control and similar applications. The integrated circuit (IC) uses
SMARTMOS technology.
The IC contains three high-side FET pre-drivers and three low-side FET pre-
drivers. Three external bootstrap capacitors provide gate charge to the high-
side FETs.
The IC interfaces to a MCU via six direct input control signals, an SPI port for
device setup and asynchronous reset, enable and interrupt signals. Both 5.0
and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are
provided.
THREE PHASE PRE-DRIVER
Features
• Extended operating range from 6.0 V to 58 V covers 12 V and 42 V systems
• Gate drive capability of 1.0 A to 2.5 A
• Fully specified from 8.0 V to 40 V covers 12 and 24 V automotive systems
• Protection against reverse charge injection from CGD and CGS of external
FETs
• Includes a charge pump to support full FET drive at low battery voltages
• Dead time is programmable via the SPI port
• Simultaneous output capability enabled via safe SPI command
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
Applications
Automotive systems
• Cooling fan
• Water pump
• Actuator controls
• Fuel pump
• Electro-hydraulic and electric power steering
• Engine control
• Motor control
VSYS
MCU
OR
DSP
33937
VPUMP
PUMP
VPWR
VLS
VSUP
PA_HS_G
PB_HS_G
PC_HS_G
VDD
PA_HS_S
VSS
PB_HS_S
PC_HS_S
3
3
3
PX_HS
PX_LS
PHASEX
PA_LS_G
CS PB_LS_G
SI PC_LS_G
SCLK
SO PX_LS_S
RST
INT
EN1
EN2
AMP_P
AMP_N
GND AMP_OUT
RSEN
Figure 1. 33937A simplified application diagram
© 2016 NXP B.V.






33937A Datasheet, Funktion
Table 2. 33937A pin definitions (continued)
Pin
Pin name Pin function
Formal name
45
PA_LS_G Power Output
Phase A Low-side
Gate Drive
46
PA_HS_S Power Input
Phase A High-side
Source
47
PA_HS_G Power Output
Phase A High-side
Gate Drive
48 PA_BOOT Analog Input Phase A Bootstrap
51
VLS
Analog
Output
VLS Regulator
54
VPWR
Power Input
Voltage Power
EP
Ground
Exposed Pad
Definition
Gate Drive for output Phase A low-side
Source connection for Phase A high-side FET
Gate Drive for output Phase A high-side
Bootstrap capacitor for Phase A
VLS regulator output. Power supply for the gate drives
Power supply input for gate drives
Device will perform as specified with the exposed pad un-terminated (floating)
however, it is recommended that the exposed pad be terminated to pin 29 (VSS)
and system ground
33937A
6
NXP Semiconductors

6 Page









33937A pdf, datenblatt
Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40 °C TA 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit Notes
Current sense amplifier (continued)
Input Offset Current
IOS • IOS = IAMP_P - IAMP_N
-80 – +80 nA
δIOS/δT
VOH
VOL
RI
ISC
CI
CMRR
Input Offset Current Drift
Output Voltage
• High Level with RLOAD = 10 kΩ to VSS
• Low Level with RLOAD = 10 kΩ to VDD
Differential Input Resistance
Output Short-circuit Current
Common Mode Input Capacitance at 10 kHz
Common Mode Rejection Ratio at DC
• CMRR = 20*Log ((VOUT_DIFF/VIN_DIFF) * (VIN_CM/VOUT_CM))
VDD-0.2
1.0
5.0
60
40
80
– pA/°C
VDD
V
0.2
– MΩ
– mA
10 pF
dB
AOL Large Signal Open Loop Voltage Gain (DC)
Nonlinearity
NL • RL = 1.0 kΩ, CL = 500 pF, 0.3 < VO < 4.8 V, Gain = 5.0 to 15
– 78 – dB
-1.0
+1.0
%
Notes
29. This parameter is a design characteristic, not production tested.
30. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
(29)
(29), (30)
(29), (30)
(29), (30)
33937A
12
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