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PDF P87C554 Data sheet ( Hoja de datos )
| Número de pieza | P87C554 | |
| Descripción | 8-bit microcontroller | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM 8 channel 10-bit A/D, I2C, PWM,
capture/compare, high I/O
Product data
Supersedes data of 1998 Aug 14
2002 Mar 25
Philips
Semiconductors
1 page  
Philips Semiconductors
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I2C, PWM,
capture/compare, high I/O
PINNING INFORMATION
Plastic Leaded Chip Carrier pin functions
9 1 61
10 60
PLASTIC
LEADED
CHIP CARRIER
26
27
44
43
Pin Function
1 P5.0/ADC0
2 VDD
3 STADC
4 PWM0
5 PWM1
6 EW
7 P4.0/CMSR0
8 P4.1/CMSR1
9 P4.2/CMSR2
10 P4.3/CMSR3
11 P4.4/CMSR4
12 P4.5/CMSR5
13 P4.6/CMT0
14 P4.7/CMT1
15 RST
16 P1.0/CT0I
17 P1.1/CT1I
18 P1.2/CT2I
19 P1.3/CT3I
20 P1.4/T2
21 P1.5/RT2
22 P1.6/SCL
23 P1.7/SDA
Pin Function
24 P3.0/RxD
25 P3.1/TxD
26 P3.2/INT0
27 P3.3/INT1
28 P3.4/T0
29 P3.5/T1
30 P3.6/WR
31 P3.7/RD
32 NC
33 NC
34 XTAL2
35 XTAL1
36 VSS
37 VSS
38 NC
39 P2.0/A08
40 P2.1/A09
41 P2.2/A10
42 P2.3/A11
43 P2.4/A12
44 P2.5/A13
45 P2.6/A14
46 P2.7/A15
Pin Function
47 PSEN
48 ALE/PROG
49 EA/VPP
50 P0.7/AD7
51 P0.6/AD6
52 P0.5/AD5
53 P0.4/AD4
54 P0.3/AD3
55 P0.2/AD2
56 P0.1/AD1
57 P0.0/AD0
58 AVref–
59 AVref+
60 AVSS
61 AVDD
62 P5.7/ADC7
63 P5.6/ADC6
64 P5.5/ADC5
65 P5.4/ADC4
66 P5.3/ADC3
67 P5.2/ADC2
68 P5.1/ADC1
SU00208
LOGIC SYMBOL
VSS
VDD
XTAL1
XTAL2
EA/VPP
ALE/PROG
PSEN
AVSS
AVDD
AVref+
AVref–
STADC
PWM0
PWM1
ADC0-7
CMSR0-5
CMT0
CMT1
RST
EW
Product data
P87C554
LOW ORDER
ADDRESS AND
DATA BUS
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
HIGH ORDER
ADDRESS AND
DATA BUS
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
SU00210
2002 Mar 25
3
5 Page 
Philips Semiconductors
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I2C, PWM,
capture/compare, high I/O
Product data
P87C554
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM
MEMORY
ALE
PSEN
PORT 0 PORT 1
Idle
Internal
1
1
Data
Data
Idle
External
1
1
Float
Data
Power-down
Internal
0
0
Data
Data
Power-down
External
0
0
Float
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
PORT 4
Data
Data
Data
Data
PWM0/
PWM1
High
High
High
High
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC
level on the P87C554 rises from 0 to 5 V. The POF bit can be set or
cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after powerdown. The VCC level
must remain above 3 V for the POF to remain unaffected by the VCC
level.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate
the possibility of an unexpected write when Idle is terminated by
reset, the instruction following the one that invokes Idle should not
be one that writes to a port pin or to external memory.
ONCE™ Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Reduced EMI Mode
The ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output.
It will automatically become active when required for external
memory accesses and resume to the OFF state after completing the
external memory access.
765432
PCON
(87H)
SMOD1 SMOD0 POF
WLE
GF1
GF0
(MSB)
10
PD IDL
(LSB)
BIT
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
SYMBOL
SMOD1
SMOD0
POF
WLE
GF1
GF0
PD
IDL
FUNCTION
Double Baud rate bit. When set to logic 1, the baud rate is doubled when the serial port SIO0 is being
used in modes 1, 2, or 3.
Selects SM0/FE for SCON.7 bit.
Power Off Flag
Watchdog Load Enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is
cleared when timer T3 is loaded.
General-purpose flag bit.
General-purpose flag bit.
Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high.
Idle mode bit. Setting this bit activates the Idle mode.
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00X00000).
Figure 3. Power Control Register (PCON)
SU00954
2002 Mar 25
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet P87C554.PDF ] | |
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