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PDF PC5566 Data sheet ( Hoja de datos )
| Número de pieza | PC5566 | |
| Descripción | Microcontroller | |
| Fabricantes | e2v | |
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Datasheet
PC5566
Microcontroller
This document provides electrical specifications, pin assignments, and package diagrams for the
PC5566 microcontroller device. For functional characteristics, refer to the MPC5566 Microcontroller
Reference Manual from Freescale. Other Freescale documents related to MPC5566 apply.
1. Overview
The PC5566 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the
Power Architecture® embedded technology. This family of parts has many new features coupled with
high performance CMOS technology to provide substantial reduction of cost per feature and significant
performance improvement over the MPC500 family.
The host processor core of this device complies with the Power Architecture embedded category that is
100% user-mode compatible (including floating point library) with the original PowerPC instruction
set.The embedded architecture enhancements improve the performance in embedded applications. The
core also has additional instructions, including digital signal processing (DSP) instructions, beyond the
original PowerPC instruction set.
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565x.
The host processor core of the PC5566 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The PC5566 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and three-
megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the PC5566 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action
hardware channels, variable number of parameters per channel, angle clock hardware, and additional
control and arithmetic instructions. The eTPU is programmed using a high-level programming language.
e2v semiconductors SAS 2014
Visit our website: www.e2v.com
for the latest version of the datasheet
1120B–BDC–05/14
1 page  
PC5566
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for
the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a
ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal
resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the
thermal performance. When the clearance between the vias leave the planes virtually disconnected, the
thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB × PD)
where:
TJ = junction temperature (C)
TB = board temperature at the package perimeter (C/W)
RJB = junction-to-board thermal resistance (C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable
value for the junction temperature is predictable. Ensure the application board is similar to the thermal
test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-
ambient thermal resistance:
RJA = RJC + RCA
where:
RJA = junction-to-ambient thermal resistance (C/W)
RJC = junction-to-case thermal resistance (C/W)
RCA = case-to-ambient thermal resistance (C/W)
e2v semiconductors SAS 2014
1120B–BDC–05/14
5
5 Page 
PC5566
2.7.1
2.7.2
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 2-5, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
Power-Up Sequence (VRC33 Grounded)
The 1.5V VDD power supply must rise to 1.35V before the 3.3V VDDSYN power supply and the RESET
power supply rises above 2.0V. This ensures that digital logic in the PLL for the 1.5V power supply does
not begin to operate below the specified operation range lower limit of 1.35V. Because the internal 1.5V
POR is disabled, the internal 3.3V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0V, VDD must be within specification before the 3.3V POR and the RESET
POR negate.
Figure 2-2. Power-Up Sequence (VRC33 Grounded)
VDDSYN and RESET Power
2.0 V
1.35 V
VDD
2.7.3
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0V before the VDD power
increases to its operating range. This ensures that the digital 1.5V logic, which is reset only by an ORed
POR and can cause the 1.5V supply to decrease less than its specification value, resets correctly. See
Table 2-5, footnote 1.
e2v semiconductors SAS 2014
1120B–BDC–05/14
11
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