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PDF CB35000 Data sheet ( Hoja de datos )
| Número de pieza | CB35000 | |
| Descripción | HCMOS STANDARD CELLS | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® CB35000 SERIES
HCMOS STANDARD CELLS
FEATURES
s 0.5 micron triple layer metal HCMOS5S pro-
cess featuring retrograde well technology,
low resistance salicided active areas, polysi-
licide gates and thin metal oxide.
s 3.3 V optimized transistor with 5 V I/O inter-
face capability
s 2 - input NAND delay of 210 ps (typ) with
fanout = 2.
s Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
s High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
s Generators to support SPRAM, DPRAM,
ROM and MULT with BIST options.
s Extensive embedded function library includ-
ing DSP and ST micros, popular third party
micros and Synopsys synthetic libraries.
PRELIMINARY DATA
s Fully independent power and ground config-
urations for inputs, core and outputs.
s I/O ring capability up to 800 pads.
s Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
s Active pull up and pull down devices.
s Buskeeper I/O functions.
s Oscillators for wide frequency spectrum.
s Broad range of 300 SSI cells.
s Low Power / Low Drive library subset.
s Design For Test includes IEEE 1149.1 JTAG
Boundary Scan architecture built in.
s Cadence and Mentor based design system
with interfaces from multiple workstations.
s Broad ceramic and plastic package range.
s Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
July 1995
Table 1 Module Generator Library
Cell
SPRAM
DPRAM
ROM
MULT
Description
256K bits max
16K word max 64 bit max
Zero static current
Tristate outputs
128K bits max
8K word max 64 bit max
Zero static current
Tristate outputs
2M bits max
32K word max 64 bit max
Diffusion programmable
Tristate outputs
Parallel asynchronous operation
2’s complement product
6 to 64 bits for both inputs
Ripple Carry or Fast Carry Look Ahead
1/16
1 page  
CB35000 SERIES
MPUL
Vdd + 0.3 Volts
LPUL
0.8 * Vdd
Trip Level = 0.5 * Vdd
Typical Current from all Vdd
supplies at LPUL or MPDL
25 µA per receiver
Figure 4a
D.C. Specifications for
LVCMOS Input Receivers
0.2 * Vdd
Vss - 0.3 Volts
MPDL
LPDL
MPUL
LPUL
Trip Level = 1.4 Volts
(nominal)
Vdd + 0.3 Volts
Vss + 2.0 Volts
Typical Current from all Vdd
supplies at LPUL or MPDL
25 µA per receiver
Figure 4b
D.C. Specifications for
LVTTL Input Receivers
Vss + 0.8 Volts
Vss - 0.3 Volts
MPDL
LPDL
Table 2 I/O Drive Capacity for LVCMOS and
LVTTL Slew Rate Buffers
Current Drive
(mA)
2.0
4.0
8.0
12.0
16.0
24.0
Maximum
Capacitance (pF)
50
100
200
300
400
800
®
Table 3 I/O Drive Capacity for LVCMOS and
LVTTL Non Slew Rate Buffers
Current Drive
(mA)
2.0
4.0
8.0
12.0
16.0
24.0
Maximum
Capacitance (pF)
50
100
200
300
400
800
5/16
5 Page 
Figure 8
SGS-THOMSON Design Flow
HARDWARE DESCRIPTION
LANGUAGE
VHDL / HDL
LOGIC SYNTHESIS
SYNOPSYS
GATE LEVEL SIMULATION
VERILOG-XL
MENTOR
SYSTEM HILO
VSS
TSSI
CURRENTEST
SIGN OFF SIMULATION
SGS-THOMSON
CB35000 SERIES
FUNCTIONAL
SIMULATION
VHDL / HDL
SCHEMATIC CAPTURE
CADENCE
MENTOR
FLOORPLANNING
DELAY EVALUATION
RC BACK ANNOTATION
CLOCK TREE SYNTHESIS
LAYOUT
SILICON
11/16
®
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CB35000.PDF ] | |
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