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Teilenummer | EMD08N10E |
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Beschreibung | Field Effect Transistor | |
Hersteller | Excelliance MOS | |
Logo | ||
Gesamt 6 Seiten N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
100V
D
RDSON (MAX.)
7.5mΩ
ID
130A
G
UIS, Rg 100% Tested
S
Pb‐Free Lead Plating
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
EMD08N10E
LIMITS
UNIT
Gate‐Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH, ID=90A, RG=25Ω
L = 0.05mH
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
VGS
ID
IDM
IAS
EAS
EAR
PD
Tj, Tstg
±30
130
93
540
90
405
202
227
90
‐55 to 150
V
A
mJ
W
°C
100% UIS testing in condition of VD=50V, L=0.1mH, VG=10V, IL=60A, Rated VDS=100V N-CH
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
MAXIMUM
UNIT
Junction‐to‐Case
RJC
Junction‐to‐Ambient
RJA
1Pulse width limited by maximum junction temperature.
2Duty cycle 1%
0.55
62.5
°C / W
2015/9/15
p.1
Outline Drawing
Dimension in mm
EMD08N10E
Dimension A b b1 c c2 E L1 L2 L3 L4 ø e f g h
Min.
4.20 0.70 0.90 0.30 1.10 9.80 2.55 6.10 14.80 13.50 3.40 2.35 1.30 3.40 2.40
Max.
4.80 1.10 1.50 0.70 1.50 10.50 2.85 6.50 15.40 14.50 3.80 2.75 1.90 3.80 3.00
2015/9/15
p.6
6 Page | ||
Seiten | Gesamt 6 Seiten | |
PDF Download | [ EMD08N10E Schematic.PDF ] |
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