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PDF P090WD-0A03 Data sheet ( Hoja de datos )
| Número de pieza | P090WD-0A03 | |
| Descripción | TFT LCD | |
| Fabricantes | MEO | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P090WD-0A03 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Issue Date: Jan .23,2007
Model No.:P090WD-0A03
Preliminary
TFT LCD Preliminary Specification
Model No.:P090WD-0A03
Customer :
Approval by:
Note:
1
Version 1.0
1 page  
Issue Date: Jan .23,2007
Model No.:P090WD-0A03
Preliminary
2.0 ABSOLUTE MAXIMUM RATINGS
2.1 Electrical Absolute Rating
2.1.1 TFT LCD Module
Item
Symbol
DVDD
VGH
Power supply voltage
VGL
VGH - VGL
AVDD
VCOM
Analog Signal Input Level VR, VG, VB
Logic Signal Input Level
VI
Min.
-0.3
-0.3
-20
-0.3
-0.3
-1.6
-0.2
-0.3
Max.
6.0
40
0.3
40
7.0
5.2
AVDD+0.2
DVDD +0.3
Unit
V
V
V
V
V
V
V
V
Note
GND=0
GND=0
GND=0
AGND=0
Note
(1) Permanent damage may occur to the LCD module if beyond this specification.
Functional operation should be restricted to the conditions described under
normal operating conditions.
(2) Ta =25±2℃
2.2 Back-Light Unit
Item
Lamp current
Lamp frequency
Symbol
IL
fL
Min.
--
9.9
Max.
160
10.5
Unit Note
mA (1) (2)
V (1) (2) (3)
Note
(1) Permanent damage may occur to the LCD module if beyond this specification.
Functional operation should be restricted to the conditions described under
normal operating conditions.
(2) Ta =25±2℃
(3) Test Condition：LED current 160mA
2.3 Environment Absolute Rating
Item
Symbol
Operating Temperature
Storage Temperature
Topa
Tstg
Min.
-20
-30
Max.
70
80
Unit
℃
℃
Note
5
Version 1.0
5 Page 
Issue Date: Jan .23,2007
Model No.:P090WD-0A03
Preliminary
5.0 INTERFACE PIN CONNECTION
5.1 TFT LCD Module
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Signal
GND
VCC
VGL
VGH
STVD
STVU
CKV
U/D
OEV
VCOM
VCOM
L/R
MOD
OEH
STHL
STHR
CPH3
CPH2
CPH1
VCC
GND
VR
VG
VB
AVDD
AVSS
I/O Description
- GND for logic circuit
I Logic power for gate driver
I Negative power for gate driver
I Positive power for gate driver
I/O Vertical start pulse
I/O Vertical start pulse
I Shift clock input for gate driver
I UP/DOWN scan setting
I Output enable input for gate driver
I Common electrode driving signal
I Common electrode driving signal
I LEFT/RIGHT shift setting
I Sequential or simultaneous sampling setting
I Output enable input for source driver
I/O Horizontal start pulse
I/O Horizontal start pulse
I Sampling and shifting CLK pulse
I Sampling and shifting CLK pulse
I Sampling and shifting CLK pulse
I Logic power for source driver
- GND for logic circuit
I Alternated video input, R
I Alternated video input, G
I Alternated video input, B
I Supply voltage for analog circuit
- Ground for analog circuit
Note
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(2)
(2)
Note (1) Selection of scanning mode (please refer to the following table)
Setting of scan control
input
IN/OUT state for start pulse
Scanning direction
U/D L/R STVD STVU STHR STHL
GND DVDD Output Input Output Input Up to down, and from left to right.
DVDD GND Input Output Input Output down to up, and from right to left.
GND GND Output Input Input Output Up to down, and from right to left.
DVDD DVDD Input Output Output Input down to up, and from left to right.
Note (2) MOD=H: Simultaneous sampling.(Please check CPH2 and CPH3 to GND when MOD=H)
MOD=L : Sequential sampling.
11
Version 1.0
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet P090WD-0A03.PDF ] | |
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