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Teilenummer | CAT93C57 |
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Beschreibung | 2K-Bit Microwire Serial EEPROM | |
Hersteller | Catalyst Semiconductor | |
Logo | ||
Gesamt 9 Seiten CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
FEATURES
s High Speed Operation:
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
s Low Power CMOS Technology
s 1.8 to 6.0 Volt Operation
s Selectable x8 or x16 Memory Organization
s Self-Timed Write Cycle with Auto-Clear
s Hardware and Software Write Protection
s Power-Up Inadvertant Write Protection
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
s Sequential Read (except 93C46)
s Program Enable (PE) Pin (93C86 only)
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial E2PROM memory devices which are configured
as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
CMOS E2PROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
CS 1
SK 2
DI 3
DO 4
8 VCC
NC (PE*) 1
7 NC (PE*)
VCC
2
6 ORG
CS 3
5 GND
SK 4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S) SOIC Package (K)
CS 1
SK 2
DI 3
DO 4
8 VCC
CS 1
7 NC (PE*) SK 2
6 ORG
DI 3
5 GND
DO 4
8 VCC
7 NC (PE*)
6 ORG
5 GND
TSSOP Package (U)
CS 1
SK 2
DI 3
DO 4
8
7
6
5
VCC
NC (PE*)
ORG
GND
*Only For 93C86
PIN FUNCTIONS
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
PE* Program Enable
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
BLOCK DIAGRAM
VCC
GND
ORG
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
DI
MODE DECODE
CS LOGIC
PE*
CLOCK
SK GENERATOR
93C46/56/57/66/86
F01
ADDRESS
DECODER
OUTPUT
BUFFER
DO
93C46/56/57/66/86 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Note: This note is applicable only to 93C86. The Write,
Erase, Write all and Erase all instructions require PE=1.
If PE is left floating, 93C86 is in Program Enabled mode.
For Write Enable and Write Disable instruction PE=don’t
care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46/
56/57/66/86 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1)
For the 93C56/57/66/86, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address auto-
matically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ
mode, only the initial data word is preceeded by a
dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46/56/57/66/86 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
Figure 2b. Read Instruction Timing (93C56/57/66/86)
SK
1 11 1 111 11 1 1 1 1 1 1
CS
AN AN–1
DI
11
0
A0
Don't Care
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
CS
AN AN-1
DI 1 0 1
A0 DN
HIGH-Z
DO
Doc. No. 25056-00 2/98 M-1
6
tCS
STATUS
VERIFY
D0
STANDBY
tSV BUSY
READY
tEW
tHZ
HIGH-Z
93C46/56/57/66/86 F05
6 Page | ||
Seiten | Gesamt 9 Seiten | |
PDF Download | [ CAT93C57 Schematic.PDF ] |
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