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CAT93C56KE Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT93C56KE
Beschreibung 2K-Bit Microwire Serial EEPROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 9 Seiten
CAT93C56KE Datasheet, Funktion
CAT93C56/57 (Die Rev. E)
2K-Bit Microwire Serial EEPROM
FEATURES
ALOGEN FR
LEA D F REETM
I High speed operation: 1MHz
I Low power CMOS technology
I 1.8 to 6.0 volt operation
I Selectable x8 or x16 memory organization
I Self-timed write cycle with auto-clear
I Hardware and software write protection
I Power-up inadvertant write protection
I 1,000,000 Program/erase cycles
I 100 year data retention
I Commercial, industrial and automotive
temperature ranges
I Sequential read
I “Green” package option available
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data reten-
tion of 100 years. The devices are available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (J,W)
NC
VCC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S,V)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (K,X)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TSSOP Package (U,Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TDFN Package (RD4, ZD4)
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
Bottom View
FUNCTIONAL SYMBOL
VCC
ORG
CS
SK
NC
DI
DO
GND
PIN FUNCTIONS
Pin Name
CS
Function
Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. M






CAT93C56KE Datasheet, Funktion
CAT93C56/57
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical 1state.
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57
write and clear instructions, and will prevent any
accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical 1state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
CS
AN AN-1
DI 1 1 1
A0
STATUS VERIFY
tCS
STANDBY
tSV tHZ
HIGH-Z
DO BUSY READY
HIGH-Z
tEW
Doc. No. 1088, Rev. M
6

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