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Teilenummer | WF43CTIBEDA |
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Beschreibung | Display Module | |
Hersteller | Winstar | |
Logo | ||
Gesamt 29 Seiten Winstar Display Co., LTD
華凌光電股份有限公司
住址: 407 台中市中清路 163 號
No.163 Chung Ching RD.,
Taichune, Taiwan, R.O.C
WEB: http://www.winstar.com.tw
E-mail: [email protected]
Tel:886-4-24262208 Fax:886-4-24262207
SPECIFICATION
CUSTOMER :
MODULE NO.:
WF43CTIBEDA#000
APPROVED BY:
( FOR CUSTOMER USE ONLY )
PCB VERSION:
SALES BY
APPROVED BY
CHECKED BY
DATA:
PREPARED BY
VERSION
DATE
REVISED
SUMMARY
PAGE NO.
0 2011.01.31
First issue
第 1 頁,共 29 頁
2.Block Diagram
TFT PANEL
480(R.G.B)X272
output 27.9V
/20mA
VDD
RBG 6/6/6 ,EN,CLK,DISP
Backlight
circuit
TFT Controller
Control-Board
8 Bits Data Bus
16 Bits Data Bus
第 6 頁,共 29 頁
6 Page 7.2 MCU Interface Timing
7.2.1 Parallel 6800-series Interface Timing
Table 7-4: Parallel 6800-series Interface Timing Characteristics (Use CS# as clock)
Symbol
fMCLK
tMCLK
tPWCSH
tPWCSL
tAS
tAH
tDSW
tDHW
tPLW
tPHW
tPLWR
tACC
tDHR
tR
tF
Parameter
System Clock Frequency*
System Clock Period*
Control Pulse High Write
Width
Read
Control Pulse Low Write (next write cycle)
Width
Write (next read cycle)
Read
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Low Time
Write High Time
Read Low Time
Data Access Time
Output Hold time
Rise Time
Fall Time
Min
1
1/ fMCLK
13
30
13
80
80
2
2
4
1
14
14
38
32
1
-
-
Typ
-
-
1.5* tMCLK
3.5* tMCLK
1.5* tMCLK
9* tMCLK
9* tMCLK
-
-
-
-
-
-
-
-
-
-
-
Max Unit
110 MHz
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
0.5 ns
0.5 ns
* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)
Figure 7-1: Parallel 6800-series Interface Timing Diagram (Use CS# as Clock)
第 12 頁,共 29 頁
12 Page | ||
Seiten | Gesamt 29 Seiten | |
PDF Download | [ WF43CTIBEDA Schematic.PDF ] |
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