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PDF CAT64LC10 Data sheet ( Hoja de datos )
| Número de pieza | CAT64LC10 | |
| Descripción | 1K/2K/4K-Bit SPI Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
s SPI bus compatible
s Low power CMOS technology
s 2.5V to 6.0V operation
s Self-timed write cycle with auto-clear
s Hardware reset pin
s Hardware and software write protection
ALOGEN FR
LEA D F REETM
s Commercial, industrial and automotive
temperature ranges
s Power-up inadvertant write protection
s RDY/BSY pin for end-of-write indication
s 1,000,000 program/erase cycles
s 100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
CS 1
SK 2
DI 3
DO 4
8 VCC
RDY/BUSY
7 RDY/BUSY
VCC
6 RESET
CS
5 GND
SK
1
2
3
4
8 RESET
7 GND
6 DO
5 DI
TSSOP Package (U, Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 RDY/BUSY
6 RESET
5 GND
SOIC Package (S, V)
TSSOP Package (UR, YR)
CS 1
SK 2
DI 3
DO 4
8 VCC
RDY/BUSY 1
7 RDY/BUSY
6 RESET
VCC 2
CS 3
5 GND
SK 4
8 RESET
7 GND
6 DO
5 DI
PIN FUNCTIONS
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC +2.5V to +6.0V Power Supply
GND
Ground
RESET
Reset
RDY/BUSY
Ready/BUSY Status
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
BLOCK DIAGRAM
VCC
GND
MEMORY ARRAY
64/128/256 x 16
ADDRESS
DECODER
DI
RESET
CS
SK
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO RDY/BUSY
64LC10/20/40 F02
Doc. No. 1021, Rev. B
1
1 page  
INSTRUCTION SET
Instruction
Read
64LC10
64LC20
64LC40
Write
64LC10
64LC20
64LC40
Write Enable
Write Disable
[Write All Locations](1)
Opcode
10101000
10101000
10101000
10100100
10100100
10100100
10100011
10100000
10100001
CAT64LC10/20/40
Address
A5 A4 A3 A2 A1 A0 0 0
A6 A5 A4 A3 A2 A1 A0 0
A7 A6 A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0 0 0
A6 A5 A4 A3 A2 A1 A0 0
A7 A6 A5 A4 A3 A2 A1 A0
XXXXXXXX
XXXXXXXX
XXXXXXXX
Data
D15 - D0
D15 - D0
D15 - D0
D15 - D0
D15 - D0
D15 - D0
D15–D0
Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF)
VCC x 0.8
VCC x 0.2
INPUT PULSE LEVELS
VCC x 0.7
VCC x 0.3
REFERENCE POINTS
Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
(3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8.
(4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
5 Doc. No. 1021, Rev. B
5 Page 
PACKAGING INFORMATION
8-LEAD TSSOP (U)
3.0 + 0.1
-A-
85
6.4
3.2
PIN #1 IDENT.
1
1.1 MAX TYP
4.4 + 0.1
-B-
0.2 C B A
4 ALL LEAD TIPS
0.1 C
ALL LEAD TIPS
(0.9)
CAT64LC10/20/40
7.72 TYP
4.16 TYP
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.09 - 0.20 TYP
-C-
0.65 TYP
0.10 + 0.05 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
GAGE PLANE
0.25
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
11 Doc. No. 1021, Rev. B
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CAT64LC10.PDF ] | |
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