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C8051F38C Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F38C
Beschreibung Full Speed USB Flash MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F38C Datasheet, Funktion
C8051F380/1/2/3/4/5/6/7/C
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F380/1/2/3/C only)
Up to 500 ksps
Built-in analog multiplexer with single-ended and
differential mode
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input option
- Two comparators
- Internal voltage reference (C8051F380/1/2/3/C only)
- Brown-out detector and POR Circuitry
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 2.7 to 5.25 V supported using On-Chip
Voltage Regulators
High Speed 8051 μC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 48 MIPS operation
- Expanded interrupt handler
Memory
- 4352 or 2304 Bytes RAM
- 64, 32, or 16 kB Flash; In-system programmable in
512-byte sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, two I2C/SMBus™, and two
enhanced UART serial ports
- Six general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F380/2/4/6)
- 32-pin LQFP (C8051F381/3/5/7/C)
- 5x5 mm 32-pin QFN (C8051F381/3/5/7/C)
Temperature Range: –40 to +85 °C
Rev. 1.4 10/13
Copyright © 2013 by Silicon Laboratories
C8051F380/1/2/3/4/5/6/7/C






C8051F38C Datasheet, Funktion
C8051F380/1/2/3/4/5/6/7/C
22.1. Supporting Documents .................................................................................. 206
22.2. SMBus Configuration..................................................................................... 206
22.3. SMBus Operation .......................................................................................... 206
22.3.1. Transmitter Vs. Receiver....................................................................... 207
22.3.2. Arbitration.............................................................................................. 207
22.3.3. Clock Low Extension............................................................................. 207
22.3.4. SCL Low Timeout.................................................................................. 207
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 208
22.4. Using the SMBus........................................................................................... 208
22.4.1. SMBus Configuration Register.............................................................. 208
22.4.2. SMBus Timing Control Register............................................................ 210
22.4.3. SMBnCN Control Register .................................................................... 214
22.4.3.1. Software ACK Generation ............................................................ 214
22.4.3.2. Hardware ACK Generation ........................................................... 214
22.4.4. Hardware Slave Address Recognition .................................................. 217
22.4.5. Data Register ........................................................................................ 221
22.5. SMBus Transfer Modes................................................................................. 223
22.5.1. Write Sequence (Master) ...................................................................... 223
22.5.2. Read Sequence (Master) ...................................................................... 224
22.5.3. Write Sequence (Slave) ........................................................................ 225
22.5.4. Read Sequence (Slave) ........................................................................ 226
22.6. SMBus Status Decoding................................................................................ 226
23. UART0 ................................................................................................................... 232
23.1. Enhanced Baud Rate Generation.................................................................. 233
23.2. Operational Modes ........................................................................................ 234
23.2.1. 8-Bit UART ............................................................................................ 234
23.2.2. 9-Bit UART ............................................................................................ 235
23.3. Multiprocessor Communications ................................................................... 236
24. UART1 ................................................................................................................... 240
24.1. Baud Rate Generator .................................................................................... 241
24.2. Data Format................................................................................................... 242
24.3. Configuration and Operation ......................................................................... 243
24.3.1. Data Transmission ................................................................................ 243
24.3.2. Data Reception ..................................................................................... 243
24.3.3. Multiprocessor Communications ........................................................... 244
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 250
25.1. Signal Descriptions........................................................................................ 251
25.1.1. Master Out, Slave In (MOSI)................................................................. 251
25.1.2. Master In, Slave Out (MISO)................................................................. 251
25.1.3. Serial Clock (SCK) ................................................................................ 251
25.1.4. Slave Select (NSS) ............................................................................... 251
25.2. SPI0 Master Mode Operation ........................................................................ 251
25.3. SPI0 Slave Mode Operation .......................................................................... 253
25.4. SPI0 Interrupt Sources .................................................................................. 254
25.5. Serial Clock Phase and Polarity .................................................................... 254
6 Rev. 1.4

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C8051F38C pdf, datenblatt
C8051F380/1/2/3/4/5/6/7/C
List of Registers
SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 53
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 54
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 54
SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 55
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 56
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 56
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 57
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 57
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select ..................................... 60
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select ................................. 61
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 63
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 67
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 68
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 69
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 70
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 72
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 73
SFR Definition 9.1. REG01CN: Voltage Regulator Control .......................................... 75
SFR Definition 10.1. PCON: Power Control .................................................................. 78
SFR Definition 11.1. DPL: Data Pointer Low Byte ........................................................ 85
SFR Definition 11.2. DPH: Data Pointer High Byte ....................................................... 85
SFR Definition 11.3. SP: Stack Pointer ......................................................................... 86
SFR Definition 11.4. ACC: Accumulator ....................................................................... 86
SFR Definition 11.5. B: B Register ................................................................................ 86
SFR Definition 11.6. PSW: Program Status Word ........................................................ 87
SFR Definition 12.1. PFE0CN: Prefetch Engine Control .............................................. 88
SFR Definition 14.1. EMI0CN: External Memory Interface Control .............................. 96
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration ..................... 97
SFR Definition 14.3. EMI0TC: External Memory TIming Control ................................ 103
SFR Definition 15.1. SFRPAGE: SFR Page ............................................................... 111
SFR Definition 16.1. IE: Interrupt Enable .................................................................... 121
SFR Definition 16.2. IP: Interrupt Priority .................................................................... 122
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 ............................................ 123
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 ............................................ 124
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2 ............................................ 125
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2 ............................................ 126
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO ........................................... 128
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 132
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 134
SFR Definition 18.1. PSCTL: Program Store R/W Control ......................................... 139
SFR Definition 18.2. FLKEY: Flash Lock and Key ...................................................... 140
SFR Definition 18.3. FLSCL: Flash Scale ................................................................... 141
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 144
Rev. 1.4
12

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