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C8051F964 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F964
Beschreibung Ultra Low Power 128K LCD MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F964 Datasheet, Funktion
C8051F96x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power Consumption at 3.6 V
- 130 µA/MHz Low-Power Active mode with dc-dc
enabled
- 120 nA sleep current w/ data retention; POR monitor
enabled
- 450 nA sleep mode with SmaRTClock
(internal LFO)
- 600 nA sleep mode with SmaRTClock (ext. crystal)
- 2 µs wakeup time; 1.5 µA analog settling time
12-Bit; 16 Ch. Analog-to-Digital Converter
- Up to 75 ksps (12-bit mode) or 300 ksps
(10-bit mode)
- External pin or internal VREF (no ext cap required)
- On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
- Autonomous burst mode with 16-bit auto-averaging
accumulator
- Integrated temperature sensor
Two Low Current Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
Internal 6-Bit Current Reference
- Up to ±500 µA; source and sink capability
- Enhanced resolution via PWM interpolation
Integrated LCD Controller
- Supports up to 128 segments (32x4)
- LCD controller consumes only 400 nA for
32-segment static display
- Integrated charge pump for contrast control
Metering-Specific Peripherals
- DC-DC buck converter allows dynamic voltage
scaling for maximum efficiency (250 mW output)
- Sleep-mode pulse accumulator with programmable
switch, de-bounce and pull-up control; interfaces
directly to metering sensor
- Data Packet Processing Engine (DPPE) includes
hardware AES, DMA, CRC and encoding blocks for
acceleration of wireless protocols
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Memory
- Up to 128 kB Flash; In-system programmable; Full
read/write/erase functionality over supply range
- Up to 8 kB internal data RAM
Digital Peripherals
- 57 or 34 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
- Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
- Precision Internal oscillator: 24.5 MHz, 2% accuracy
supports UART operation; spread-spectrum mode
for reduced EMI
- Low power internal oscillator: 20 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz
internal LFO
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides 4 breakpoints, single stepping
Packages
- 76-pin DQFN (6 x 6 mm)
- 40-pin QFN (6 x 6 mm)
- 80-pin TQFP (12 x 12 mm)
Temperature Range: –40 to +85 °C
C2CK/RST
VBAT
VDC
VBATDC
IND
GNDDC
CAP
GND
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051
Controller Core
128k Byte ISP Flash
Program Memory
256 Byte SRAM
8092 Byte XRAM
C2D
VBAT
VDD
VREG
Analog
Power
Digital
Power
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
DMA
CRC
Engine
AES
Engine
Encoder
SYSCLK
LCD Charge
Pump
Low Power
20 MHz
Oscillator
XTAL1
XTAL2
External
Oscillator
Circuit
XTAL3
XTAL4
Enhanced
smaRTClock
Oscillator
System Clock
Configuration
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1, 2, 3
PCA/WDT
SMBus
Priority
Crossbar
Decoder
SPI 0
SPI 1
(DMA Enabled)
Crossbar Control
LCD (up to 4x32)
EMIF
Pulse Counter
Analog Peripherals
Internal External
VREF VREF
12-bit
75ksps
ADC
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A +
-
CP1, CP1A +
-
Comparators
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
P3-6
Drivers
P7
Driver
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5/INT5
P1.6/INT6
P1.7
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
P2.5
P2.6
P2.7
32
P3.0...P6.7
16
P7.0/C2D
Rev. 1.0 7/13
Copyright © 2013 by Silicon Laboratories
C8051F96x






C8051F964 Datasheet, Funktion
C8051F96x
15. Encoder/Decoder ................................................................................................. 207
15.1. Manchester Encoding.................................................................................... 208
15.2. Manchester Decoding.................................................................................... 209
15.3. Three-out-of-Six Encoding............................................................................ 210
15.4. Three-out-of-Six Decoding ............................................................................ 211
15.5. Encoding/Decoding with SFR Access ........................................................... 212
15.6. Decoder Error Interrupt.................................................................................. 212
15.7. Using the ENC0 module with the DMA.......................................................... 213
16. Special Function Registers................................................................................. 216
16.1. SFR Paging ................................................................................................... 216
16.2. Interrupts and SFR Paging ............................................................................ 216
17. Interrupt Handler.................................................................................................. 232
17.1. Enabling Interrupt Sources ............................................................................ 232
17.2. MCU Interrupt Sources and Vectors.............................................................. 232
17.3. Interrupt Priorities .......................................................................................... 233
17.4. Interrupt Latency............................................................................................ 233
17.5. Interrupt Register Descriptions ...................................................................... 235
17.6. External Interrupts INT0 and INT1................................................................. 242
18. Flash Memory....................................................................................................... 244
18.1. Programming the Flash Memory ................................................................... 244
18.1.1. Flash Lock and Key Functions .............................................................. 244
18.1.2. Flash Erase Procedure ......................................................................... 244
18.1.3. Flash Write Procedure .......................................................................... 245
18.1.4. Flash Write Optimization ....................................................................... 246
18.2. Non-volatile Data Storage ............................................................................. 247
18.3. Security Options ............................................................................................ 247
18.4. Determining the Device Part Number at Run Time ....................................... 249
18.5. Flash Write and Erase Guidelines ................................................................. 250
18.5.1. VDD Maintenance and the VDD Monitor .............................................. 250
18.5.2. PSWE Maintenance .............................................................................. 251
18.5.3. System Clock ........................................................................................ 251
18.6. Minimizing Flash Read Current ..................................................................... 252
19. Power Management ............................................................................................. 257
19.1. Normal Mode ................................................................................................. 258
19.2. Idle Mode....................................................................................................... 258
19.3. Stop Mode ..................................................................................................... 259
19.4. Low Power Idle Mode .................................................................................... 259
19.5. Suspend Mode .............................................................................................. 263
19.6. Sleep Mode ................................................................................................... 263
19.7. Configuring Wakeup Sources........................................................................ 264
19.8. Determining the Event that Caused the Last Wakeup................................... 264
19.9. Power Management Specifications ............................................................... 268
20. On-Chip DC-DC Buck Converter (DC0).............................................................. 269
20.1. Startup Behavior............................................................................................ 270
20.4. Optimizing Board Layout ............................................................................... 271
5 Rev. 1.0

6 Page









C8051F964 pdf, datenblatt
C8051F96x
Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 105
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 106
Figure 7.3. Comparator Hysteresis Plot ................................................................ 107
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 112
Figure 8.1. CIP-51 Block Diagram ......................................................................... 115
Figure 9.1. C8051F96x Memory Map .................................................................... 124
Figure 9.2. Flash Program Memory Map ............................................................... 125
Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126
Figure 10.1. Multiplexed Configuration Example ................................................... 134
Figure 10.2. Non-multiplexed Configuration Example ........................................... 135
Figure 10.3. EMIF Operating Modes ..................................................................... 135
Figure 10.4. Non-multiplexed 16-bit MOVX Timing ............................................... 139
Figure 10.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 140
Figure 10.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 141
Figure 10.7. Multiplexed 16-bit MOVX Timing ....................................................... 142
Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 143
Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 144
Figure 11.1. DMA0 Block Diagram ........................................................................ 147
Figure 12.1. CRC0 Block Diagram ........................................................................ 160
Figure 12.2. Bit Reverse Register ......................................................................... 167
Figure 13.1. Polynomial Representation ............................................................... 168
Figure 14.1. AES Peripheral Block Diagram ......................................................... 176
Figure 14.2. Key Inversion Data Flow ................................................................... 179
Figure 14.3. AES Block Cipher Data Flow ............................................................. 185
Figure 14.4. Cipher Block Chaining Mode ............................................................. 190
Figure 14.5. CBC Encryption Data Flow ................................................................ 191
Figure 14.6. CBC Decryption Data Flow ............................................................... 195
Figure 14.7. Counter Mode .................................................................................... 198
Figure 14.8. Counter Mode Data Flow .................................................................. 199
Figure 16.1. SFR Page Stack ................................................................................ 217
Figure 18.1. Flash Security Example ..................................................................... 247
Figure 19.1. C8051F96x Power Distribution .......................................................... 258
Figure 19.2. Clock Tree Distribution ...................................................................... 259
Figure 20.1. Step Down DC-DC Buck Converter Block Diagram .......................... 269
Figure 22.1. Reset Sources ................................................................................... 278
Figure 22.2. Power-On Reset Timing Diagram ..................................................... 279
Figure 23.1. Clocking Sources Block Diagram ...................................................... 286
Figure 23.2. 25 MHz External Crystal Example ..................................................... 288
Figure 24.1. SmaRTClock Block Diagram ............................................................. 295
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 303
Figure 25.1. Pulse Counter Block Diagram ........................................................... 312
Figure 25.2. Mode Examples ................................................................................. 313
Figure 25.3. Reed Switch Configurations .............................................................. 314
Figure 25.4. Debounce Timing .............................................................................. 318
Figure 25.5. Flutter Example ................................................................................. 320
11 Rev. 1.0

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