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R4F2463 Schematic ( PDF Datasheet ) - Renesas

Teilenummer R4F2463
Beschreibung 16-Bit Single-Chip Microcomputer
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R4F2463 Datasheet, Funktion
REJ09B0403-0200
www.DataSheet4U.com
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16 H8S/2472, H8S/2463, H8S/2462 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2472 R4F2472
H8S/2463 R4F2463
H8S/2462 R4F2462
Rev.2.00
Revision Date: Aug. 20, 2008






R4F2463 Datasheet, Funktion
Preface
www.DataSheet4U.com
The H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group products are single-chip
microcomputers made up of the high-speed H8S/2600 CPU employing Renesas Technology
original architecture as its core, and the peripheral functions required to configure a system. The
H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs.
Target Users: This manual was written for users who will be using the H8S/2472 Group,
H8S/2463 Group, and H8S/2462 Group in the design of application systems. Target
users are expected to understand the fundamentals of electrical circuits, logical
circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group to
the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a
detailed description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 29,
List of Registers.
Examples: Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Rev. 2.00 Aug. 20, 2008 Page vi of xlviii

6 Page









R4F2463 pdf, datenblatt
6.8 Bus Arbitration .................................................................................................................. 157
6.8.1 Overview ......................................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m...... 157
6.8.2 Operation .............................................................................................................. 157
6.8.3 Bus Mastership Transfer Timing .......................................................................... 158
Section 7 Data Transfer Controller (DTC)........................................................161
7.1 Features.............................................................................................................................. 161
7.2 Register Descriptions ......................................................................................................... 163
7.2.1 DTC Mode Register A (MRA) ............................................................................. 164
7.2.2 DTC Mode Register B (MRB).............................................................................. 165
7.2.3 DTC Source Address Register (SAR)................................................................... 165
7.2.4 DTC Destination Address Register (DAR)........................................................... 165
7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 166
7.2.6 DTC Transfer Count Register B (CRB)................................................................ 166
7.2.7 DTC Enable Registers (DTCER).......................................................................... 166
7.2.8 DTC Vector Register (DTVECR)......................................................................... 167
7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 168
7.2.10 Event Counter Control Register (ECCR).............................................................. 169
7.2.11 Event Counter Status Register (ECS) ................................................................... 170
7.3 DTC Event Counter ........................................................................................................... 171
7.3.1 Event Counter Handling Priority .......................................................................... 173
7.3.2 Usage Notes .......................................................................................................... 173
7.4 Activation Sources............................................................................................................. 174
7.5 Location of Register Information and DTC Vector Table ................................................. 175
7.6 Operation ........................................................................................................................... 177
7.6.1 Normal Mode........................................................................................................ 178
7.6.2 Repeat Mode......................................................................................................... 179
7.6.3 Block Transfer Mode ............................................................................................ 180
7.6.4 Chain Transfer ...................................................................................................... 181
7.6.5 Interrupt Sources................................................................................................... 182
7.6.6 Operation Timing.................................................................................................. 182
7.6.7 Number of DTC Execution States ........................................................................ 184
7.7 Procedures for Using DTC................................................................................................. 185
7.7.1 Activation by Interrupt.......................................................................................... 185
7.7.2 Activation by Software ......................................................................................... 185
7.8 Examples of Use of the DTC ............................................................................................. 186
7.8.1 Normal Mode........................................................................................................ 186
7.8.2 Software Activation .............................................................................................. 187
7.9 Usage Notes ....................................................................................................................... 188
7.9.1 Module Stop Mode Setting ................................................................................... 188
Rev. 2.00 Aug. 20, 2008 Page xii of xlviii

12 Page





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