CAT525 Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT525 | |
| Description | Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications | |
| Manufacturers | Catalyst Semiconductor | |
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CAT525
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
APPLICATIONS
s Four 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
s Independent reference inputs
s Buffered wiper outputs
s Non-volatile NVRAM memory wiper storage
s Output voltage range includes both supply rails
s 4 independently addressable buffered
output wipers
s 1 LSB accuracy, high resolution
s Serial µP interface
s Single supply operation: 2.7V-5.5V
s Setting read-back without effecting outputs
DESCRIPTION
The CAT525 is a quad 8-Bit digitally programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax ma-
chines and cellular telephones on automated high vol-
ume production lines and systems capable of self cali-
bration, it is also well suited for applications were equip-
ment requiring periodic adjustment is either difficult to
access or located in a hazardous environment.
The CAT525 offers four independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail op amps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically rein-
s Automated product calibration
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in
self-calibrating and adaptive control systems
s Tamper-proof calibrations
s DAC (with memory) substitute
stated when power is returned. Each wiper can be
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP’s output.
Control of the CAT525 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT525's to share a common serial interface and
communications back to the host controller is via a single
serial data line thanks to the CAT525’s Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of non-volatile NVRAM Memory Erase/Write cycle.
The CAT525 is available in the 0°C to 70°C commercial
and –40°C to 85°C industrial operating temperature
ranges and offered in 20-pin plastic DIP and Surface
mount packages.
FUNCTIONAL DIAGRAM
VREF H1 VREF H3
VREF H2
VREF H4
2 1 20 19
RDY/BSY
5
PROG
9
PROGRAM
CONTROL
+
–
CLK
4
6
CS
7
DATA
CONTROLLER
CAT525
H.V.
CHARGE
PUMP
NVRAM
+
–
+
–
SERIAL
DATA
OUTPUT
REGISTER
+
–
7K
(ea)
11 12 13 14
VREFL2 VREFL4
VREFL1 VREFL3
18
VOUT1
17
VOUT2
16
VOUT3
15
VOUT4
8
DO
PIN CONFIGURATION
DIP Package (P)
VREF H2
VREF H1
DVD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
1 20
2 19
3 18
4 17
5 16
6 15
CAT525
7 14
8 13
9 12
10 11
VREF H3
VREF H4
VOUT1
VOUT2
VOUT3
VOUT4
VREF L4
VREF L3
VREF L2
VREF L1
SOIC Package (J)
VREF H2
VREF H1
DVD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
1 20
2 19
3 18
4 17
5 16
6 15
CAT525
7 14
8 13
9 12
10 11
VREF H3
VREF H4
VOUT1
VOUT2
VOUT3
VOUT4
VREF L4
VREF L3
VREF L2
VREF L1
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25078-00 4/01-A M-1
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CAT525
PIN DESCRIPTION
Pin Name
Function
1 VREFH2 Maximum DAC 2 output voltage
2 VREFH1 Maximum DAC 1 output voltage
3 VDD
Power supply positive
4 CLK
Clock input pin
5 RDY/BSY Ready/Busy output
6 CS
Chip select
7 DI
Serial data input pin
8 DO
Serial data output pin
9 PROG
EEPROM Programming Enable
Input
10 GND
Power supply ground
11 VREFL1
Minimum DAC 1 output voltage
12 VREFL2
Minimum DAC 2 output voltage
13 VREFL3
14 VREFL4
Minimum DAC 3 output voltage
Minimum DAC 4 output voltage
15 VOUT4
DAC 4 output
16 VOUT3
DAC 3 output
17 VOUT2
18 VOUT1
19 VREFH4
DAC 2 output
DAC 1 output
Maximum DAC 4 output voltage
20 VREFH3
Maximum DAC 3 output voltage
DAC addressing is as follows:
DAC OUTPUT
VOUT1
VOUT2
VOUT3
VOUT4
A0
0
1
0
1
A1
0
0
1
1
DEVICE OPERATION
The CAT525 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be adjusted without altering the stored
output setting, which is useful for testing new output
settings before storing them in memory.
DIGITAL INTERFACE
The CAT525 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
5
CHIP SELECT
Chip Select (CS) enables and disables the CAT525’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT525’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT525’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
Doc. No. 25078-00 4/01 - A M-1
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT525 electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CAT525.PDF Datasheet ] | |
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