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C8051F507 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F507
Beschreibung Mixed Signal ISP Flash MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F507 Datasheet, Funktion
Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz;
- Typical stop mode current: 2 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F50x/F51x
Mixed Signal ISP Flash MCU Family
Memory
- 4352 bytes internal data RAM (256 + 4096 XRAM)
- 64 or 32 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 40, 33, or 25 Port I/O; All 5 V tolerant
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 48-Pin QFP/QFN (C8051F500/1/4/5)
- 40-Pin QFN (C8051F508/9-F510/1)
- 32-Pin QFP/QFN (C8051F502/3/6/7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
64 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
4 kB XRAM
POR WDT
Rev. 1.2 3/11
Copyright © 2011 by Silicon Laboratories C8051F500/1/2/3/4/5/6/7/8/9-F510/1






C8051F507 Datasheet, Funktion
C8051F50x/F51x
21.5. Sleep Mode and Wake-Up ............................................................................ 207
21.6. Error Detection and Handling ........................................................................ 207
21.7. LIN Registers................................................................................................. 208
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 208
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 210
22. Controller Area Network (CAN0) ........................................................................ 218
22.1. Bosch CAN Controller Operation................................................................... 219
22.1.1. CAN Controller Timing .......................................................................... 219
22.1.2. CAN Register Access............................................................................ 220
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 220
22.2. CAN Registers............................................................................................... 222
22.2.1. CAN Controller Protocol Registers........................................................ 222
22.2.2. Message Object Interface Registers ..................................................... 222
22.2.3. Message Handler Registers.................................................................. 222
22.2.4. CAN Register Assignment .................................................................... 223
23. SMBus................................................................................................................... 226
23.1. Supporting Documents .................................................................................. 227
23.2. SMBus Configuration..................................................................................... 227
23.3. SMBus Operation .......................................................................................... 227
23.3.1. Transmitter vs. Receiver ....................................................................... 228
23.3.2. Arbitration.............................................................................................. 228
23.3.3. Clock Low Extension............................................................................. 228
23.3.4. SCL Low Timeout.................................................................................. 228
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 229
23.4. Using the SMBus........................................................................................... 229
23.4.1. SMBus Configuration Register.............................................................. 229
23.4.2. SMB0CN Control Register .................................................................... 233
23.4.3. Data Register ........................................................................................ 236
23.5. SMBus Transfer Modes................................................................................. 236
23.5.1. Write Sequence (Master) ...................................................................... 237
23.5.2. Read Sequence (Master) ...................................................................... 238
23.5.3. Write Sequence (Slave) ........................................................................ 239
23.5.4. Read Sequence (Slave) ........................................................................ 240
23.6. SMBus Status Decoding................................................................................ 240
24. UART0 ................................................................................................................... 243
24.1. Baud Rate Generator .................................................................................... 243
24.2. Data Format................................................................................................... 245
24.3. Configuration and Operation ......................................................................... 246
24.3.1. Data Transmission ................................................................................ 246
24.3.2. Data Reception ..................................................................................... 246
24.3.3. Multiprocessor Communications ........................................................... 247
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 252
25.1. Signal Descriptions........................................................................................ 253
25.1.1. Master Out, Slave In (MOSI)................................................................. 253
25.1.2. Master In, Slave Out (MISO)................................................................. 253
6 Rev. 1.2

6 Page









C8051F507 pdf, datenblatt
C8051F50x/F51x
Table 21.3. Autobaud Parameters Examples ........................................................ 205
Table 21.4. LIN Registers (Indirectly Addressable) ............................................... 210
Table 22.1. Background System Information ........................................................ 220
Table 22.2. Standard CAN Registers and Reset Values ....................................... 223
Table 23.1. SMBus Clock Source Selection .......................................................... 230
Table 23.2. Minimum SDA Setup and Hold Times ................................................ 231
Table 23.3. Sources for Hardware Changes to SMB0CN ..................................... 235
Table 23.4. SMBus Status Decoding ..................................................................... 241
Table 24.1. Baud Rate Generator Settings for Standard Baud Rates ................... 244
Table 25.1. SPI Slave Timing Parameters ............................................................ 264
Table 27.1. PCA Timebase Input Options ............................................................. 288
Table 27.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules ........................................................ 290
Table 27.3. Watchdog Timer Timeout Intervals1 ................................................... 299
12 Rev. 1.2

12 Page





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