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C8051F564 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F564
Beschreibung Mixed Signal ISP Flash MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F564 Datasheet, Funktion
Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz
- Typical stop mode current: 1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F55x/56x/57x
Mixed Signal ISP Flash MCU Family
Memory
- 2304 bytes internal data RAM (256 + 2048 XRAM)
- 32 or 16 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 33, 25, or 18 Port I/O; All 5 V tolerant
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 40-pin QFN (C8051F568-9 and ‘F570-5)
- 32-pin QFP/QFN (C8051F560-7)
- 24-pin QFN (C8051F550-7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
2 kB XRAM
POR WDT
Rev. 1.2 9/14
Copyright © 2014 by Silicon Laboratories C8051F55x, C8051F56x, C8051F57x






C8051F564 Datasheet, Funktion
C8051F55x/56x/57x
21.2.2. Message Object Interface Registers ..................................................... 214
21.2.3. Message Handler Registers.................................................................. 214
21.2.4. CAN Register Assignment .................................................................... 215
22. SMBus................................................................................................................... 218
22.1. Supporting Documents .................................................................................. 219
22.2. SMBus Configuration..................................................................................... 219
22.3. SMBus Operation .......................................................................................... 219
22.3.1. Transmitter Vs. Receiver....................................................................... 220
22.3.2. Arbitration.............................................................................................. 220
22.3.3. Clock Low Extension............................................................................. 220
22.3.4. SCL Low Timeout.................................................................................. 220
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 221
22.4. Using the SMBus........................................................................................... 221
22.4.1. SMBus Configuration Register.............................................................. 221
22.4.2. SMB0CN Control Register .................................................................... 225
22.4.3. Data Register ........................................................................................ 228
22.5. SMBus Transfer Modes................................................................................. 228
22.5.1. Write Sequence (Master) ...................................................................... 229
22.5.2. Read Sequence (Master) ...................................................................... 230
22.5.3. Write Sequence (Slave) ........................................................................ 231
22.5.4. Read Sequence (Slave) ........................................................................ 232
22.6. SMBus Status Decoding................................................................................ 232
23. UART0 ................................................................................................................... 235
23.1. Baud Rate Generator .................................................................................... 235
23.2. Data Format................................................................................................... 237
23.3. Configuration and Operation ......................................................................... 238
23.3.1. Data Transmission ................................................................................ 238
23.3.2. Data Reception ..................................................................................... 238
23.3.3. Multiprocessor Communications ........................................................... 240
24. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 246
24.1. Signal Descriptions........................................................................................ 247
24.1.1. Master Out, Slave In (MOSI)................................................................. 247
24.1.2. Master In, Slave Out (MISO)................................................................. 247
24.1.3. Serial Clock (SCK) ................................................................................ 247
24.1.4. Slave Select (NSS) ............................................................................... 247
24.2. SPI0 Master Mode Operation ........................................................................ 248
24.3. SPI0 Slave Mode Operation .......................................................................... 250
24.4. SPI0 Interrupt Sources .................................................................................. 250
24.5. Serial Clock Phase and Polarity .................................................................... 251
24.6. SPI Special Function Registers ..................................................................... 252
25. Timers ................................................................................................................... 259
25.1. Timer 0 and Timer 1 ...................................................................................... 261
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 261
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 262
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 262
6 Rev. 1.2

6 Page









C8051F564 pdf, datenblatt
C8051F55x/56x/57x
Table 22.3. Sources for Hardware Changes to SMB0CN ..................................... 227
Table 22.4. SMBus Status Decoding ..................................................................... 233
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates ................... 236
Table 24.1. SPI Slave Timing Parameters ............................................................ 258
Table 26.1. PCA Timebase Input Options ............................................................. 282
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules ........................................................ 284
Table 26.3. Watchdog Timer Timeout Intervals1 ................................................... 293
12 Rev. 1.2

12 Page





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