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PDF CAT524 Data sheet ( Hoja de datos )
| Número de pieza | CAT524 | |
| Descripción | Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT524
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
s Four 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
s Common reference inputs
s Buffered wiper outputs
s Non-volatile NVRAM memory wiper storage
s Output voltage range includes both supply rails
s 4 independently addressable buffered
output wipers
s 1 LSB accuracy, high resolution
s Serial µP interface
s Single supply operation: 2.7V-5.5V
s Setting read-back without effecting outputs
DESCRIPTION
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are not
lost when the device is powered down and are automati-
cally reinstated when power is returned. Each wiper can
be dithered to test new output values without effecting
APPLICATIONS
s Automated product calibration
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in
self-calibrating and adaptive control systems
s Tamper-proof calibrations
s DAC (with memory) substitute
the stored settings, and stored settings can be read back
without disturbing the DPP’s output.
The CAT524 is controlled with a simple 3 wire serial
interface. A Chip Select pin allows several devices to
share a common serial interface. Communication back
to the host controller is via a single serial data line thanks
to the Tri-Stated CAT524 Data Output pin. A RDY/BSY
output working in concert with an internal low voltage
detector signals proper operation of the non-volatile
NVRAM memory Erase/Write cycle.
The CAT524 is available in the 0 to 70° C commercial
and –40° C to 85° C industrial operating temperature
ranges. Both 14-pin plastic DIP and SOIC packages are
offered.
FUNCTIONAL DIAGRAM
RDY/BSY
3
VDD
1
VREF H
14
PROG
7
PROGRAM
CONTROL
5
DI
CLK
2
4
CS
SERIAL
CONTROL
NVRAM
+
–
13
VOUT1
+ 12
– VOUT2
+ 11
– VOUT3
+ 10
– VOUT4
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
524
5 10
69
78
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREF L
GND
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
5 524 10
69
78
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREFL
GND
CAT524
8
GND
SERIAL
DATA
OUTPUT
REGISTER
9
VREFL
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
DO
1
Doc. No. 25076-00 4/01 M-1
1 page  
PIN DESCRIPTION
Pin Name Function
1 VDD Power supply positive.
2 CLK Clock input pin.Clock input pin.
3 RDY/BSY Ready/Busy Output
4 CS Chip Select
5 DI Serial data input pin.
6 DO Serial data output pin.
7 PROG EEPROM Programming Enable
Input
8
GND
Power supply ground.
9
VREFL
Minimum DAC output voltage.
10
VOUT4
DAC output channel 4.
11
VOUT3
DAC output channel 3.
12
VOUT2
DAC output channel 2.
13
VOUT1
DAC output channel 1.
14
VREFH
Maximum DAC output voltage.
CAT524
DAC addressing is as follows:
DAC OUTPUT
VOUT1
VOUT2
VOUT3
VOUT4
A0 A1
00
10
01
11
DEVICE OPERATION
The CAT524 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.
DIGITAL INTERFACE
The CAT524 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT524’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT524’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT524’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
5 Doc. No. 25076-00 Rev. 4/01
5 Page 
APPLICATION CIRCUITS (Cont.)
+12V
CAT524
1N914
1.0 µF
10K
+12V
1N914
74C14
.005 µF
VCC 13
2.5 µF
INPUT 1
20V
IN5250B
CHIP SELECT.
PROGRAM
DATA IN
DATA OUT
CLOCK
3
Vpp
1
VDD
OCPATT550244
4 CS
14
VREFH
7 PROG
5 DI
6
DO
2 CLK
VOUT 1 13
VOUT 2 12
11
VOUT 3
10
VOUT 4
9
VREFL
8
GND
1.0 µF
47K
47K
47K
47K
0.47 µF
2
IN 1
0.01 µF
TREB CAP 4
8
BASS CAP
0.39 µF
0.1 µF
19
VZ
10
OUTPUT 1
LM1040
9
LOUDNESS
14
VOLUME
11 BALANCE
5 TREBLE
16
BASS
0.22 0.22 0.22 0.22
µF µF µF µF
BYPASS
1
7
18
47 µF
10 µF
10 µF
OUT 1
15
OUTPUT 2
OUT 2
INPUT 2
0.47 µF
0.1 µF
4.7K
23 IN 2
3
STEREO
22 ENHANCE
0.39 µF
17
BASS CAP
21
TREB CAP
24 0.01 µF
GND
12
GND
Digital Stereo Control
11 Doc. No. 25076-00 Rev. 4/01
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CAT524.PDF ] | |
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