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CAT523 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT523
Beschreibung Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 10 Seiten
CAT523 Datasheet, Funktion
Advance Information
CAT523
Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications
FEATURES
s Two 8-bit DPPS Configured as Programmable
Voltages in DAC-like Applications
s Buffered Wiper Outputs
s Nonvolatile Wiper Storage
s Output voltage range includes both supply rails
s 2 independently addressable output wipers
s 1 LSB Accuracy, High Resolution
s Serial µP interface
s Single supply operation: 2.7V-5.5V
s Setting read-back without effecting outputs
APPLICATIONS
s Automated product calibration.
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
s DAC (with memory) substitute
DESCRIPTION
The CAT523 is a dual, 8-bit digitally-programmable
potentiometer configured for programmable voltage and
DAC-like applications. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines,
it is also well suited for systems capable of self
calibration, and applications where equipment which is
either difficult to access or in a hazardous environment,
requires periodic adjustment.
The 2 independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail OP
AMPS. Wiper settings, stored in non-volatile memory,
are not lost when the device is powered down and are
automatically reinstated when power is returned. Each
wiper can be dithered to test new output values without
effecting the stored settings and stored settings can be
read back without disturbing the DAC’s output.
Control of the CAT523 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT523's to share a common serial interface and
communication back to the host controller is via a single
serial data line thanks to the CAT523’s Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of non-volatile Erase/Write cycle.
The CAT523 is available in the 0 to 70° C Commercial
and –40° C to + 85° C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and SOIC
mount packages.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
PROG
7
RDY/BSY
3
PROGRAM
CONTROL
5
DI
CLK
2
4
CS
SERIAL
CONTROL
VDD
1
DATA
REGISTER
AND
NONVOLATILE
MEMORY
VREFH
14
7K
7K
+
+
13
VOUT1
12
VOUT2
DIP Package (P)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
523
5 10
69
78
VREFH
VOUT1
VOUT2
NC
NC
VREFL
GND
SOIC Package (J)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
5 523 10
69
78
VREFH
VOUT1
VOUT2
NC
NC
VREFL
GND
CAT523
8
GND
SERIAL
DATA
OUTPUT
REGISTER
9
VREF L
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
DO
1
Doc. No. 25076-00 2/98 M-1






CAT523 Datasheet, Funktion
CAT523
Advance Information
VREF
VREF, the voltage applied between pins VREFHandVREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH andVREFL are connected across the
power supply rails. When using less than the full supply
voltage VREFH is restricted to voltages between VDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
READY/BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT523 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detec-
tor circuit monitoring VDD. If VDD is below the minimum
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT523, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 523s to share a
single serial data line and simplifies interfacing multiple
523s to a microprocessor.
WRITING TO MEMORY
Programming the CAT523’s EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high some-
time after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the EEPROM cells. The CAT523’s EEPROM
memory cells will endure over 100,000 write cycles and
will retain data for a minimum of 100 years without being
refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
setting is reloaded into the DAC control register. Since
Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
N N+1 N+2
CS
DI
DO
PROG
RDY/BSY
DAC
OUTPUT
NEW DAC DATA
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS
DI 1 A0 A1
CURRENT DAC DATA
DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
DAC
OUTPUT
CURRENT
DAC VALUE
NON-VOLATILE
6

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