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CAT522 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT522
Beschreibung 8-Bit Dual Digital POT With Independent Reference Inputs
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 10 Seiten
CAT522 Datasheet, Funktion
Advanced Information
CAT522
8-Bit Dual Digital POT With Independent Reference Inputs
FEATURES
s Buffered Outputs
s Output settings retained without power
s Independent Reference Inputs
s Output range includes both supply rails
s Programming voltage generated on-chip
s 2 independently addressable outputs
s Serial µP interface
s Single supply operation: 2.7V-5.5V
DESCRIPTION
The CAT522 is a dual 8-Bit Memory DAC designed as an
electronic replacement for mechanical potentiometers
and trim pots. Intended for final calibration of products
such as camcorders, fax machines and cellular tele-
phones on automated high volume production lines and
systems capable of self calibration, it is also well suited
for applications were equipment requiring periodic ad-
justment is either difficult to access or located in a
hazardous environment.
The CAT522 offers 2 independently programmable DACs
each having its own reference inputs and each capable
of rail to rail output swing. Outputs are buffered by rail
to rail OP AMPS Output settings, stored in non-volatile
EEPROM memory, are not lost when the device is
powered down and are automatically reinstated when
power is returned. Each output can be dithered to test
new output values without effecting the stored settings
FUNCTIONAL DIAGRAM
VDD
1
RDY/BSY
3
SERIAL DATA OUTPUT
6
DO
PROG
7
PROGRAM
CONTROL
CLK
2
4
CS
DI 5
DATA
CONTROLLER
H.V.
CHARGE
PUMP
EEPROM
LATCH
DAC 1
14 VREF H1
+
12 VOUT 1
9 VREF L1
EEPROM
LATCH
DAC 2
13 VREF H2
+
11
VOUT 2
10
VREF L2
CAT522
8
GND
APPLICATIONS
s Automated product calibration.
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
and stored settings can be read back without disturbing
the DAC’s output.
Control of the CAT522 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT522's to share a common serial interface and com-
munications back to the host controller is via a single
serial data line thanks to the CAT522’s Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of EEPROM Erase/Write cycle.
The CAT522 operates from a single 3–5 volt power
supply. The high voltage required for EEPROM Erase/
Write operations is generated on-chip.
The CAT522 is available in the 0°C to 70°C Commercial
and –40°C to +85°C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and Surface
mount packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 11
CAT522
5 10
69
78
VREF H1
VREF H2
VDD
CLK
VOUT1
RDY/BSY
VOUT2
VREF L2
VREF L1
CS
DI
DO
GND
PROG
1 14
2 13
3 12
4 11
CAT522
5 10
69
78
VREF H1
VREF H2
VOUT1
VOUT2
VREF L2
VREF L1
GND
© 2000 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1






CAT522 Datasheet, Funktion
CAT522
Advanced Information
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH &VREFL are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on VREFH and
VREFL as specified in the References section of DC
Electrical Characteristics.
READY/BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT522 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detec-
tor circuit monitoring VDD. If VDD is below the minimum
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT522, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
N N+1 N+2
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 522s to share a
single serial data line and simplifies interfacing multiple
522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of generating and ramping up the program-
ming voltage for data transfer to the EEPROM cells. The
CAT522’s EEPROM memory cells will endure over
1,000,000 write cycles and will retain data for a minimum
of 100 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS
NEW DAC DATA
DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
DO D0 D1 D2 D3 D4 D5 D6 D7
CS
DI 1 A0 A1
CURRENT DAC DATA
DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
PROG
RDY/BSY
DAC
OUTPUT
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
RDY/BSY
DAC
OUTPUT
CURRENT
DAC VALUE
NON-VOLATILE
8/00 6

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