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CAT35C704 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT35C704
Beschreibung 4K-Bit Secure Access Serial E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 14 Seiten
CAT35C704 Datasheet, Funktion
Preliminary
CAT35C704
4K-Bit Secure Access Serial E2PROM
FEATURES
s Single 5V Supply
s Password READ/WRITE Protection: 1 to 8 Bytes
s Memory Pointer WRITE Protection
s Sequential READ Operation
s 256 x16 or 512 x 8 Selectable Serial Memory
s High Speed Synchronous Protocol
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT35C704 is a 4K-bit Serial E2PROM that safe-
guards stored data from unauthorized access by use of
a user selectable (1 to 8 byte) access code and a
movable memory pointer. Two operating modes provide
unprotected and password-protected operation allow-
ing the user to configure the device as anything from a
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE
NC 1 16 NC
NC 2 15 NC
6 ERR
CS 3 14 VCC
5 GND CLK 4 13 PE
DI 5 12 ERR
DO 6 11 GND
NC 7 10 NC
NC 8
9 NC
PIN FUNCTIONS
5074 FHD F01
Pin Name
Function
CS Chip Select
DO(1)
Serial Data Output
CLK Clock Input
DI(1)
Serial Data Input
PE Parity Enable
ERR
Error Indication Pin
VCC +5V Power Supply
GND
Ground
Note:
(1) DI, DO may be tied together to form a common I/O.
s Operating Frequency: DC–3MHz
s Low Power Consumption:
–Active: 3 mA
–Standby: 250 µA
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
ROM to a fully protected no-access memory. The
CAT35C704 uses a unique serial-byte synchronous
communication protocol and has a Sequential Read
feature where data can be sequentially clocked out of
the memory array. The device is available in 8-pin DIP
or 16-pin SOIC packages.
BLOCK DIAGRAM
VCC
GND
DO
CLK
PE
CS
DI
SERIAL
COMMUNI-
CATION
BLOCK
ERR
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
64-BIT ACCESS CODE
&
CONTROL BLOCK
4K-BIT EEPROM
ARRAY
R/W ADDRESS
BUFFER DECODER
ADDRESS
REGISTER
STATUS
REGISTER
MEMORY
POINTER
35C704 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25045-00 2/98






CAT35C704 Datasheet, Funktion
CAT35C704
Preliminary
CLK
The System Clock is a TTL compatible input pin that
allows operation of the device over a frequency range of
DC to 3 MHz.
DI
The Data Input pin is TTL compatible and accepts data
and instructions in a serial format. Each instruction must
begin with “1” as a start bit. The device will accept as
many bytes as an instruction requires, including both
data and address bytes. With the SECS protocol, extra
bits will be disregarded if they are “0”s and misinter-
preted as the next instruction if they are “1”s. An instruc-
tion error will cause the device to abort operation and all
I/O communication will be terminated until a reset is
received.
Figure 5. Program/Erase Timing
CS
tCKH
CLK
DI
LAST ADDRESS BIT FOR ERASE
LAST OPCODE BIT FOR ERAL
LAST DATA BIT FOR WRITE/WRAL
DO HIGH-Z
tEW
tPD
DO
The Data Output pin is a tri-state TTL compatible output.
It is normally in a high impedance state unless a READ
or an ENABLE BUSY instruction is executed. Following
the completion of a 16-bit or 8-bit data stream, the output
will return to the high impedance state. During a pro-
gram/erase cycle, if the ENABLE BUSY instruction has
been previously executed, the output will stay LOW
while the device is BUSY, and it will be set HIGH when
the program/erase cycle is completed. DO will stay
HIGH until the completion of the next instruction’s op-
code and, if the next instruction is a READ, DO will output
the appropriate data at the end of the instruction. If the
ENABLE BUSY instruction has not been previously
executed, DO will stay in a high impedance state. DO will
NEXT INSTRUCTION
5074 FHD F07
Figure 6. CS to DO Status Timing
CS
CLK
DI
LAST ADDRESS BIT FOR ERASE
LAST OPCODE BIT FOR ERAL
LAST DATA BIT FOR WRITE/WRAL
DO HIGH-Z
NEXT INSTRUCTION
tCSZ
tCSD
READY
BUSY HIGH-Z BUSY
5074 FHD F08
Doc. No. 25045-00 2/98
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6 Page









CAT35C704 pdf, datenblatt
CAT35C704
Preliminary
INSTRUCTION SET
DISAC Disable Access
1000 1000
This instruction will lock the memory from all program/
erase operations regardless of the contents of the memory
pointer. A write can be accomplished only by first enter-
ing the ENAC instruction followed by a valid access
code.
ENAC Enable Access
1100 0101 [Access Code]
In the protected mode, this instruction, followed by a
valid access code, unlocks the device for read/write/
clear access.
WMPR Write Memory Pointer Register
1100 0100 [A15–A8] [A7–A0] (x8 organization)
1100 0100 [A7–A0] (x16 organization)
The WMPR instruction followed by 8 or 16 bits of
address (depending on the organization) will move the
pointer to the newly specified address.
MACC Modify Access Code
1101 [Length] [Old code] [New code]
[New code]
This instruction requires the user to enter the old access
code, if one was set previously, followed by the new
access code and a re-entry of the new access code for
verification. Within the instruction format, the variable
[Length] designates the length of the access code as the
following:
[Length] = [0] No access code. Set device to unpro-
tected mode.
[Length] = [1–8] Length of access code is 1 to 8 bytes.
[Length] = [>8] Illegal number of bytes. The CAT35C704
will ignore the rest of the transmission.
RMPR Read Memory Pointer Register
1100 1010
Output the content of the memory pointer register to the
serial output port.
OVMPR Override Memory Pointer Register
1000 0011
Override the memory protection for the next instruction.
READ Read Memory
1100 1001 [A15–A8] [A7–A0] (x8 organization)
1100 1001 [A7–A0] (x16 organization)
Output the contents of the addressed memory location
to the serial port.
WRITE Write Memory
1100 0001 [A15–A8] [A7–A0] [D7–D0] (x8 organization)
1100 0001 [A7–A0] [D15–D8] [D7–D0] (x16 organization)
Write the 8 bit or 16 bit data to the addressed memory
location. After the instruction, address, and data have
been entered, the self-timed program/erase cycle will
start. The addressed memory location will be erased
before data is written. The DO pin may be used to output
the RDY/BUSY status by having previously entered the
ENBSY instruction. During the program/erase cycle, DO
will output a LOW for BUSY during this cycle and a HIGH
for READY after the cycle has been completed.
ERASE Clear Memory
1100 0000 [A15–A8] [A7–A0] (x8 organization)
1100 0000 [A7–A0] (x16 organization)
Erase data in the specified memory location (set memory
to “1”). After the instruction and the address have been
entered, the self-timed clear cycle will start. The DO pin
may be used to output the RDY/BUSY status by having
previously entered the ENSBY instruction. During the
clear cycle, DO will output a LOW for BUSY during this
cycle and a HIGH for ready after the cycle has been
completed.
ERAL Clear All
1000 1001
1000 1001
Erase the data of all memory locations (all cells set to
“1”). For protection against inadvertent chip clear, the
ERAL instruction is required to be entered twice.
WRAL Write All
1000 1001
1100 0011 [D15–D8] [D7–D0] (x16 organization)
1000 1001
1100 0011 [D7–D0] (x8 organization)
Write one or two bytes of data to all memory locations.
An ERAL will be automatically performed before the
Doc. No. 25045-00 2/98
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