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GG12864M1-04WA0 Schematic ( PDF Datasheet ) - GEMINI

Teilenummer GG12864M1-04WA0
Beschreibung LCD MODULE
Hersteller GEMINI
Logo GEMINI Logo 




Gesamt 30 Seiten
GG12864M1-04WA0 Datasheet, Funktion
LCD Module User Manual
Customer
Ordering Part Number
Outline DRAWING NO.
:
: GG12864M1-04WA0
: m-GG12864M1-04WA0_A01
Approved By Customer:
Date:
Approved By Checked By Prepared By
GEMINI Technology Co., Ltd.
ADD: RM1521 Investel, 1123-2 Sanbon-Dong, Gunpo-City, Kyeonggi-Do, Korea
TEL: 0082-31-455-3200(Rep.) FAX:0082-31-343-2100
Http://www.findlcd.com
GG12864M1-04WA0_A01
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GG12864M1-04WA0 Datasheet, Funktion
7.Interface Description
Parallel interface,8080 series
Pin No.
1
2
3
4
Symbol
/CS1
/RES
A0
/WR
Level Description
L Chip select input pins.ActiveLow
L When /RST is "L", initialization is executed.
Register select input pin
H/L A0 = "H": Indicates that "A0" are display data
A0 = "L": Indicates that "A0" are control data
H/L Write signal. Low active .
5 /RD H/L When connected to an 8080 MPU, this is Read signal. Low active.
6~13 DB0~DB7 H/L Data bus DB0~DB7
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29(RED)
30(Black)
VDD
VSS
VOUT
CAP3+
CAP1-
CAP1+
CAP2+
CAP2-
V1
V2
V3
V4
V0
NC
IRS
A
K
3.0V Power supply for Logic
0V Ground
--- DC/DC converter. Connect a capacitor to ground
--- DC/DC converter. Connect a capacitor to CAP1-
--- DC/DC converter. Connect a capacitor to CAP1+
--- DC/DC converter. Connect a capacitor to CAP1-
--- DC/DC converter. Connect a capacitor to CAP2-
--- DC/DC converter. Connect a capacitor to CAP2+
--- Voltage levels for LCD. Connect a capacitor to ground
--- Voltage levels for LCD. Connect a capacitor to ground
--- Voltage levels for LCD. Connect a capacitor to ground
--- Voltage levels for LCD. Connect a capacitor to ground
--- Voltage levels for LCD. Connect a capacitor to ground
--- No Connection
This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
H/L IRS = “L”: Do not use the internal resistors. The V0 voltage level is
regulated by an external resistive voltage divider attached to the VR
terminal
+3.0V Anode of LED Backlight
0V Cathode of LED Backlight
GG12864M1-04WA0_A01
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GG12864M1-04WA0 pdf, datenblatt
Serial Interface (PS = "L", RS=0 Ohms,RP open)
When the ST7565P is active, serial data (DB7) and serial clock (DB6) inputs are enabled.
And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data
can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel
data on the eighth serial clock. Serial data input is display data when A0(RS) is high and
control data when A0(RS) is low. Since the clock signal (DB6) is easy to be affected by the
external noise caused by the line length, the operation check on the actual machine is
recommended.
Figure 3. Serial Interface Protocol
Busy Flag (For parallel interface only)
The Busy Flag indicates whether the LCM is operating or not. When DB7 is "H" in read
status operation, this device is in busy status and will accept only read status instruction. If
the cycle time is correct, the microprocessor needs not to check this flag before each
instruction, which improves the MPU performance.
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column
addressable array. Each pixel can be selected when the page and column addresses are
specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line
(DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to
DB7. The microprocessor can read from and write to RAM through the I/O buffer. Since the
LCD controller operates independently, data can be written into RAM at the same time as
data is being displayed without causing the LCD flicker.
Page Address Circuit
The LCM incorporates 4-bit Page A ddress register changed by only the "Set Page"
instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0 are "L") is a special RAM
area for the icons and display data DB0 is only valid.When Page Address is above 8, it is
impossible to access to on-chip RAM. See in “Display Data RAM Map”
Line Address Circuit .
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the
display. Therefore, by setting line address repeatedly, it is possible to realize the screen
scrolling and page switching without changing the contents of on-chip RAM as shown in
“Display Data RAM Map”It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame,
the contents of register are copied to the line counter which is increased by CL signal and
generates the Line Address for transferring the 132-bit RAM data to the display data latch
circuit. However, display data of icons are not scrolled because the MPU can not access
Line Address of icons.
GG12864M1-04WA0_A01
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