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CAT34RC02UETE13REV-E Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT34RC02UETE13REV-E
Beschreibung 2-kb I2C Serial EEPROM/ Serial Presence Detect
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 16 Seiten
CAT34RC02UETE13REV-E Datasheet, Funktion
CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect
FEATURES
ALOGEN FR
LEAD
F
R
E
E
TM
I 400 kHz I2C bus compatible*
I 1.7 to 5.5 volt operation
I 16-byte page write buffer
I Hardware write protection for entire memory
I Permanent and reversible software write
protection for lower 128 bytes
I Schmitt trigger on SCL and SDA inputs
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, SOIC, TSSOP and TDFN packages
I Industrial and extended temperature ranges
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP,
SOIC, TSSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J, W)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
FUNCTIONAL SYMBOL
VCC
SCL
TDFN Package (SP2, VP2)
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
A2, A1, A0
WP
CAT34RC02
VSS
SDA
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 1.7 V to 5.5 V Power Supply
VSS Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1052, Rev. K






CAT34RC02UETE13REV-E Datasheet, Funktion
CAT34RC02
WRITE OPERATIONS
Byte Write
In Byte Write mode the Master creates a START condition,
and then broadcasts the Slave address, byte address
and data to be written. The Slave acknowledges the
three bytes by pulling down the SDA line during the 9th
clock cycle following each byte. The Master creates a
STOP condition after the last ACK from the Slave, which
then starts the internal write operation (Fig. 6). During
internal write, the Slave will ignore any read/write request
from the Master.
Page Write
The CAT34RC02 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. The page is selected by the
four most significant bits of the address byte presented
to the device after the Slave address, while the four least
significant bits point to the byte within the page. By
loadingmore than one data byte into the device, up to
an entire page can be written in one write cycle (Fig. 7).
The internal byte address counter will increment after
each data byte. If the Master transmits more than 16
data bytes, then earlier bytes will be overwritten by later
bytes in a wrap-aroundfashion within the selected
page. The internal write cycle is started following the
STOP condition created by the Master.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34RC02 is busy writing or is ready to accept
commands. Polling is implemented by sending a
Selective Readcommand (described under READ
OPERATIONS) to the device. The CAT34RC02 will not
acknowledge the Slave address, as long as internal
write is in progress.
WRITE PROTECTION
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against WRITE operations
(Fig. 9). If the WP pin is left floating or is grounded. then
it has no impact on the operation of the CAT34RC02.
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against WRITE operations by setting one of
two Software Write Protection (SWP) flags/switches.
The PSWP (Permanent Software Write Protection) flag
can be set but not cleared by the user. The RSWP
(Reversible Software Write Protection) flag can be set
and cleared by the user. Whereas the PSWP flag can be
set in-system, the RSWP flag is meant to be used
during testing. RSWP commands require the presence
of a very high voltage (higher than VCC) on address pin
A0 and fixed logic levels for the other two address pins.
The CAT34RC02 is shipped unprotected. The state of
the SWP flags can be read by issuing an Immediate
Address Readcommand, with the Slave address
preambleset to 0110 (6h) instead of the normal1010
(Ah). A SWP READ will return the complemented versions
of the two flags in the last two slots of the resulting data
byte; the other six more significant bits in the data byte
have no meaning to the user (Fig. 11).
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
S
T
O
P
SDA LINE S
P
AAA
CCC
KKK
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: A
SLAVE
MASTER R ADDRESS
T
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
S
T
O
P
SDA LINE S
*
AA
CC
KK
AA
CC
KK
P
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1052, Rev. K
6

6 Page









CAT34RC02UETE13REV-E pdf, datenblatt
CAT34RC02
8-PAD TDFN 2X3 PACKAGE (VP2, SP2)
A
B
0.75 + 0.05 MAX.
PIN 1 INDEX AREA
2.00 + 0.10
(S)
2X
0.15C
2X
0.15C
0.10C
8X
0.08C
0.20 REF.
C
0.0 - 0.05
1.50 + 0.10
C0.35
DAP SIZE 1.7 X 2.1
4
0.25 + 0.05 (8X)
8X
0.10 M C AB
0.50 TYP. (6X)
1.50 REF. (2X)
1 0.30 + 0.10 (8X)
NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM.
3. WARPAGE SHALL NOT EXCEED 0.10 MM.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC.
Doc. No. 1052, Rev. K
12

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