CAT34RC02JETE13REV-E Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT34RC02JETE13REV-E | |
| Description | 2-kb I2C Serial EEPROM/ Serial Presence Detect | |
| Manufacturers | Catalyst Semiconductor | |
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CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect
FEATURES
ALOGEN FR
LEAD
F
R
E
E
TM
I 400 kHz I2C bus compatible*
I 1.7 to 5.5 volt operation
I 16-byte page write buffer
I Hardware write protection for entire memory
I Permanent and reversible software write
protection for lower 128 bytes
I Schmitt trigger on SCL and SDA inputs
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, SOIC, TSSOP and TDFN packages
I Industrial and extended temperature ranges
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP,
SOIC, TSSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J, W)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
FUNCTIONAL SYMBOL
VCC
SCL
TDFN Package (SP2, VP2)
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
A2, A1, A0
WP
CAT34RC02
VSS
SDA
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 1.7 V to 5.5 V Power Supply
VSS Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1052, Rev. K
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CAT34RC02
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two ‘wires’ are connected to the supply (VCC) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
START Condition
The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a ‘wake-up’ call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Device Addressing
The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the ‘preamble’) are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A2, A1 and A0, select one of eight possible
Slave devices. The last bit, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then ‘releases’ the SDA
line durng the 9th clock cycle. If the Master acknowledges
in the 9th clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
1
89
ACKNOWLEDGE
1 0 1 0 A2 A1 A0 R/W Normal Read and Write
DEVICE ADDRESS
0
1
1
0
A2
A1
A0
R/W
Programming the Write
Protect Register
5 Doc No. 1052, Rev. K
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT34RC02JETE13REV-E electronic component. |
| Information | Total 16 Pages | |
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| Download | [ CAT34RC02JETE13REV-E.PDF Datasheet ] | |
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