CAT28LV64KI-15T Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT28LV64KI-15T | |
| Description | 64K-Bit CMOS PARALLEL EEPROM | |
| Manufacturers | Catalyst Semiconductor | |
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CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
FEATURES
■ 3.0V to 3.6 V Supply
■ Read access times:
– 150/200/250ns
■ Low power CMOS dissipation:
– Active: 8 mA max.
– Standby: 100 µA max.
■ Simple write operation:
– On-chip address and data latches
– Self-timed write cycle with auto-clear
■ Fast write cycle time:
– 5ms max.
■ Commercial, industrial and automotive
temperature ranges
ALOGEN FR
LEA D F REETM
■ CMOS and TTL compatible I/O
■ Automatic page write operation:
– 1 to 32 bytes in 5ms
– Page load timer
■ End of write detection:
– Toggle bit
– DATA polling
■ Hardware and software write protection
■ 100,000 program/erase cycles
■ 100 year data retention
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A4
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1010, Rev. D
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Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV64
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tINIT(1)
tBLC(1)(3)
Parameter
Write Cycle Time
Address Setup Time0
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period
After Power-up
Byte Load Cycle Time
28LV64-15
Min Max
5
0
100
0
0
110
0
0
110
60
0
5 10
0.05 100
28LV64-20
Min Max
5
0
100
0
0
150
10
10
150
100
0
28LV64-25
Min Max
5
0
100
0
0
150
10
10
150
100
0
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 10 5 10 ms
0.1 100 0.1 100 µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5 Doc. No. 1010, Rev. D
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT28LV64KI-15T electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CAT28LV64KI-15T.PDF Datasheet ] | |
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