Datenblatt-pdf.com


CAT28F512 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT28F512
Beschreibung 512K-Bit CMOS Flash Memory
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 14 Seiten
CAT28F512 Datasheet, Funktion
CAT28F512
512K-Bit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 90/120/150 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
s 12.0V ± 5% Programming and Erase Voltage
s Electronic Signature
DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
s Commercial, Industrial and Automotive
Temperature Ranges
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP ( 8 x 20)
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F512 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
ERASE VOLTAGE
SWITCH
I/O0–I/O7
I/O BUFFERS
WE
CE
OE
A0–A15
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
524,288 BIT
MEMORY
ARRAY
28F512 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25042-00 2/98 F-1






CAT28F512 Datasheet, Funktion
CAT28F512
A.C. CHARACTERISTICS, Program/Erase Operation
VCC = +5V ±10%, unless otherwise specified.
JEDEC Standard
Symbol Symbol
Parameter
tAVAV
tWC Write Cycle Time
tAVWL
tAS Address Setup Time
tWLAX
tAH Address Hold Time
tDVWH
tDS Data Setup Time
tWHDX
tDH Data Hold Time
tELWL
tCS CE Setup Time
tWHEH
tCH CE Hold Time
tWLWH
tWP WE Pulse Width
tWHWL
tWPH WE High Pulse Width
tWHWH1(2)
-
Program Pulse Width
tWHWH2(2)
-
Erase Pulse Width
tWHGL - Write Recovery Time Before Read
tGHWL - Read Recovery Time Before Write
tVPEL
- VPP Setup Time to CE
Preliminary
28F512-90 28F512-12 28F512-15
Min. Max. Min. Max. Min. Max. Unit
90 120 150 ns
0 0 0 ns
40 40 40 ns
40 40 40 ns
10 10 10 ns
0 0 0 ns
0 0 0 ns
40 40 40 ns
20 20 20 ns
10 10 10 µs
9.5 9.5 9.5 ms
6 6 6 µs
0 0 0 µs
100 100 100
ns
ERASE AND PROGRAMMING PERFORMANCE(1)
Parameter
Chip Erase Time(3)(5)
28F512-90
Min. Typ. Max.
0.5 10
28F512-12
Min. Typ. Max.
0.5 10
28F512-15
Min. Typ. Max.
0.5 10
Unit
sec
Chip Program Time(3)(4)
16
16
1 6 sec
Note:
(1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched,
VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 25042-00 2/98 F-1
6

6 Page









CAT28F512 pdf, datenblatt
CAT28F512
Figure 7. Programming Algorithm(1)
START
PROGRAMMING
APPLY VPPH
INITIALIZE
ADDRESS
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
WRITE PROG. CMD
ADDR AND DATA
Preliminary
BUS
OPERATION COMMAND
COMMENTS
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
1ST WRITE
CYCLE
WRITE
SETUP
DATA = 40H
2ND WRITE PROGRAM VALID ADDRESS AND DATA
CYCLE
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE PROGRAM
CYCLE
VERIFY
DATA = C0H
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
VERIFY
DATA ?
YES
NO
INCREMENT
ADDRESS
NO LAST
ADDRESS?
YES
WRITE READ
COMMAND
NO
INC
PLSCNT
= 25 ?
YES
READ
STANDBY
READ BYTE TO VERIFY
PROGRAMMING
COMPARE DATA OUTPUT
TO DATA EXPECTED
1ST WRITE
CYCLE
READ
DATA = 00H
SETS THE REGISTER FOR
READ OPERATION
APPLY VPPL
APPLY VPPL
STANDBY
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
28F512 F09
Doc. No. 25042-00 2/98 F-1
12

12 Page





SeitenGesamt 14 Seiten
PDF Download[ CAT28F512 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CAT28F512512K-Bit CMOS Flash MemoryCatalyst Semiconductor
Catalyst Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche