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PDF CAT28C257 Data sheet ( Hoja de datos )
| Número de pieza | CAT28C257 | |
| Descripción | 256K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Advanced
CAT28C257
256K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times: 90/120/150 ns
s Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 150 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
–DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C257 is a fast, low power, 5V-only CMOS
Parallel E2PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C257 features
hardware and software write protection.
The CAT28C257 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A7–A14
VCC
CE
OE
WE
A0–A6
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25073-00 2/98
1 page  
Advanced
CAT28C257
A.C. CHARACTERISTICS, Write Cycle
VCC=5V±10%, unless otherwise specified
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(3
tOES
tOEH
tWP(3)
tDS
tDH
tINIT(1)
tBLC(1)(4)
Parameter
28C257-90
Min. Max.
Write Cycle Time
5
Address Setup Time
0
Address Hold Time
50
CE Setup Time
0
CE Hold Time
0
CE Pulse Time
100
OE Setup Time
0
OE Hold Time
0
WE Pulse Width
100
Data Setup Time
50
Data Hold Time
0
Write Inhibit Period After Power-up 5
10
Byte Load Cycle Time
0.1 100
28C257-12
Min. Max.
5
0
50
0
0
100
0
0
100
50
0
5 10
0.1 100
28C257-15
Min. Max.
5
0
50
0
0
100
0
0
100
50
0
5 10
0.1 100
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Figure 1. A.C. Testing Input/Output Waveform(2)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
5096 FHD F04
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
5 Doc. No. 25073-00 2/98
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT28C257.PDF ] | |
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