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PDF CAT28C17A Data sheet ( Hoja de datos )
| Número de pieza | CAT28C17A | |
| Descripción | 16K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28C17A
16K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times: 200 ns
s Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 100 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time: 10ms Max
s End of Write Detection:
–DATA Polling
–RDY/BSY Pin
s Hardware Write Protection
s CMOS and TTL Compatible I/O
s 10,000 Program/Erase Cycles
s 10 Year Data Retention
s Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C17A is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and a RDY/BSY pin signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C17A features hardware write protection.
The CAT28C17A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 28-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
A4–A10
VCC
CE
OE
WE
A0–A3
RDY/BUSY
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
& RDY/BUSY
COLUMN
DECODER
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
2,048 x 8
E2PROM
ARRAY
I/O BUFFERS
I/O0–I/O7
5091 FHD F02
Doc. No. 25034-00 2/98
1 page  
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V ±10%, unless otherwise specified.
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tDL
tINIT(1)
tDB
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Data Latch Time
Write Inhibit Period After Power-up
Time to Device Busy
CAT28C17A
28C17A-20
Min. Max.
10
10
100
0
0
150
15
15
150
50
10
50
5 20
80
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
5 Doc. No. 25034-00 2/98
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CAT28C17A.PDF ] | |
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