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CAT25C256 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT25C256
Beschreibung 128K/256K-Bit SPI Serial CMOS E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 11 Seiten
CAT25C256 Datasheet, Funktion
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E2PROM
FEATURES
s 5 MHz SPI Compatible
s 1.8 to 6.0 Volt Operation
s Hardware and Software Protection
s Zero Standby Current
s Low Power CMOS Technology
s SPI Modes (0,0 &1,1)
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Self-Timed Write Cycle
s 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s 64-Byte Page Write Buffer
s Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E2PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan-
tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro-
tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
SOIC Package (S, K) TSSOP Package (U14) DIP Package (P)
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SOIC Package (S16)
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS 7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
NC 3
NC 4
NC 5
NC 6
WP 7
VSS 8
16 VCC
15 HOLD
14 NC
13 NC
12 NC
11 NC
10 SCK
9 SI
PIN FUNCTIONS
TSSOP Package (U20)
NC 1
CS 2
SO 3
SO 4
NC 5
NC 6
WP 7
VSS 8
NC 9
NC 10
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 NC
11 NC
SO
SI
CS
WP
HOLD
SCK
Pin Name
SO
SCK
WP
VCC
VSS
CS
SI
HOLD
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
STATUS
REGISTER
XDEC
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
NC No Connect
Note: CAT25C256 not available in 8-Lead S or U packages.
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25088-00 1/01






CAT25C256 Datasheet, Funktion
CAT25C128/256
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
STATUS REGISTER
7654
WPEN
X
X
X
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
3210
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1 BPO
00
01
10
11
Array Address
Protected
25C128
25C256
None
None
3000-3FFF
6000-7FFF
2000-3FFF
4000-7FFF
0000-3FFF
0000-7FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Doc. No. 25088-00 1/01
6

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