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CAT25C16 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT25C16
Beschreibung 1K/2K/4K/8K/16K SPI Serial CMOS E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 10 Seiten
CAT25C16 Datasheet, Funktion
Advanced Information
CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS E2PROM
FEATURES
s 10 MHz SPI Compatible
s 1.8 to 6.0 Volt Operation
s Hardware and Software Protection
s Zero Standby Current
s Low Power CMOS Technology
s SPI Modes (0,0 & 1,1)
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Self-Timed Write Cycle
s 8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP
s 16/32-Byte Page Write Buffer
s Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS E2PROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s ad-
vanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C01/02/04 fea-
tures a 16-byte page write buffer. The 25C08/16 fea-
tures a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
PIN CONFIGURATION
TSSOP Package (U14) SOIC Package (S)
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is de-
signed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/
14-pin TSSOP packages.
DIP Package (P)
TSSOP Package (U)
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS 7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
PIN FUNCTIONS
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
MSOP Package (R)*
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*CAT 25C01/02 only
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
VSS
BLOCK DIAGRAM
1
2
3
4
WORD ADDRESS
BUFFERS
8 VCC
7 HOLD
6 SCL
5 SI
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
Pin Name
SO
SCK
WP
Function
Serial Data Output
Serial Clock
Write Protect
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
XDEC
E2PROM
ARRAY
VCC
VSS
CS
SI
HOLD
NC
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
BLOCK
PROTECT
LOGIC
STATUS
REGISTER
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25067-00 5/00






CAT25C16 Datasheet, Funktion
CAT25C01/02/04/08/16
Advanced Information
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04/08/16 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable
Figure 2. WREN Instruction Timing
CS
writes(reset the latch) to the device. Disabling writes
will protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04/08/
16, followed by the 16-bit address for 25C08/16. (only
10-bit addresses are used for 25C08, 11-bit addresses
are used for 25C16. The rest of the bits are don't care
bits) and 8-bit address for 25C01/02/04 (for the 25C04,
bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially by
continuing to provide clock pulses. The internal ad-
dress pointer is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to 0000h allowing the read cycle to be
continued indefinitely. The read operation is terminated
by pulling the CS high. To read the status register,
RDSR instruction should be sent. The contents of the
status register are shifted out on the SO line. The status
register may be read at any time even during a write
cycle. Read sequece is illustrated in Figure 4. Reading
status register is illustrated in Figure 5.
SK
SI
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
0 0 0 0 0 1 10
HIGH IMPEDANCE
SK
SI
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
0 0 0 0 0 1 00
HIGH IMPEDANCE
6

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