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PDF W78E58B Data sheet ( Hoja de datos )
| Número de pieza | W78E58B | |
| Descripción | 8 BIT MICROCONTROLLER | |
| Fabricantes | Winbond | |
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W78E58B
8-BIT MICROCONTROLLER
1. GENERAL DESCRIPTION
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The
W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-
bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78E58B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E58B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
• Fully static design 8-bit CMOS microcontroller
• 32K bytes of in-system programmable Flash EPROM for Application Program (APROM)
• 4K bytes of auxiliary ROM for Loader Program (LDROM)
• 512 bytes of on-chip RAM (including 256 bytes of AUX-RAM, software selectable)
• 64K bytes program memory address space and 64K bytes data memory address space
• Four 8-bit bi-directional ports
• One 4-bit multipurpose programmable port
• Three 16-bit timer/counters
• One full duplex serial port
• Eight-sources, two-level interrupt capability
• Built-in power management
• Code protection
• Packaged in
− DIP 40: W78E58B-24/40
− PLCC 44: W78E58BP-24/40
− QFP 44: W78E58BF-24/40
Publication Release Date: March 18, 2002
- 1 - Revision A3
1 page  
W78E58B
• AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Example,
CHPENR REG F6H
CHPCON REG BFH
MOV CHPENR, #87H
MOV CHPENR, #59H
ORL CHPCON, #00010000B ; enable AUX-RAM
MOV CHPENR, #00H
MOV R0, #12H
MOV A, #34H
MOVX @R0, A
; Write 34h data to 12h address.
Timers 0, 1 and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
Clock
The W78E58B is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E58B relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78E58B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
Publication Release Date: March 18, 2002
- 5 - Revision A3
5 Page 
W78E58B
P4 REGISTER
P4.x
READ
WRITE
P4xCSINV
DATA I/O
RD_CS
MUX 4->1
WR_CS
RD/WR_CS
ADDRESS BUS
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
Selectable
comparator
REGISTER
P4xCMP0
P4xCMP1
P4xFUN0
P4xFUN1
P4.x INPUT DATA BUS
PIN
P4.x
In-System Programming (ISP) Mode
The W78E58B equips one 32K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E58B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register. The CHPCON is read-only by default, software must write two specific values 87H, then
59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute. The W78E58B achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device needs
proper time to complete the ISP operations before awaken from idle mode, software may use timer
interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
applications, the in-system programming feature make it possible to easily update the system firmware
without opening the chassis.
- 11 -
Publication Release Date: March 18, 2002
Revision A3
11 Page | ||
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| PDF Descargar | [ Datasheet W78E58B.PDF ] | |
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