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CAT24WC64 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24WC64
Beschreibung 32K/64K-Bit I2C Serial CMOS E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 8 Seiten
CAT24WC64 Datasheet, Funktion
Preliminary
CAT24WC32/64
32K/64K-Bit I2C Serial CMOS E2PROM
FEATURES
s 400 KHz I2C Bus Compatible*
s 1.8 to 6 Volt Read and Write Operation
s Cascadable for up to Eight Devices
s 32-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s 8-Pin DIP or 8-Pin SOIC
s Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
s Zero Standby Current
s Commercial, Industrial and Automotive
Temperature Ranges
s Write Protection
– Entire Array Protected When WP at VIH
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
CAT24WC32/64 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SOIC Package (J,K)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
24WC32/64 F01
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
256
E2PROM
XDEC 128/256 128/256 X 256
Pin Name
Function
A0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
SCL
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC32/64 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25053-00 2/98 S-1






CAT24WC64 Datasheet, Funktion
CAT24WC32/64
Preliminary
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC32/64. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC32/64 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC32/64 writes up to 32 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24WC32/64 will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC32/64 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC32/64 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC32/64 is still busy with the
write operation, no ACK will be returned. If
CAT24WC32/64 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC32/64
will accept both slave and byte addresses, but the
Figure 6. Byte Write Timing
S
T
BUS ACTIVITY: A SLAVE
MASTER R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
DATA
S
T
O
P
SDA LINE S
X XX *
P
A A AA
C C CC
K K KK
24WC32/64 F08
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
X XX *
A
C
K
A
C
K
* = Don't care bit for 24WC32
X= Don't care bit
A
C
K
DATA
DATA n
DATA n+31
S
T
O
P
P
A AA A
C CC C
K KK K
24WC32/64 F09
Doc. No. 25053-00 2/98 S-1
6

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