CAT24WC33 Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT24WC33 | |
| Description | 32K/64K-Bit I2C Serial CMOS E2PROM | |
| Manufacturers | Catalyst Semiconductor | |
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Preliminary
CAT24WC33/65
32K/64K-Bit I2C Serial CMOS E2PROM
FEATURES
s 400 KHz I2C Bus Compatible*
s 1.8 to 6 Volt Read and Write Operation
s Cascadable for up to Eight Devices
s 32-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s 8-Pin DIP or 8-Pin SOIC
s Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
s Zero Standby Current
s Commercial, Industrial and Automotive Tem-
perature Ranges
s Write Protection
–Bottom 1/4 Array Protected When WP at VIH
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SOIC Package (J,K)
A0
A1
A2
VSS
1
2
3
4
PIN FUNCTIONS
8 VCC
7 WP
6 SCL
5 SDA
24WC33/65 F01
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
256
E2PROM
XDEC 128/256 128/256 X 256
Pin Name
Function
A0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
SCL
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC33/65 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25064-00 2/98 S-1
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Preliminary
CAT24WC33/65
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 32K/64K devices may
to be connected to the same bus. These bits must
compare to the hardwired input pins, A2, A1 and A0. The
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC33/65 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC33/65 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv-
ing each 8-bit byte.
When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
5020 FHD F06
5027 FHD F07
5 Doc. No. 25064-00 2/98 S-1
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT24WC33 electronic component. |
| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CAT24WC33.PDF Datasheet ] | |
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