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CAT24WC32 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24WC32
Beschreibung 32K/64K-Bit I2C Serial CMOS E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 12 Seiten
CAT24WC32 Datasheet, Funktion
CAT24WCt43U2.c/o6m432K/64K-Bit I2C Serial CMOS EEPROM
heeFEATURES
taSI 400 KHz I2C bus compatible*
aI 1.8 to 5.5 volt read and write operation
.DI Cascadable for up to eight devices
wI 32/64-Byte page write buffer
wI Self-timed write cycle with auto-clear
w I 8-pin DIP or 8-pin SOIC
mI Schmitt trigger inputs for noise protection
.coDESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
Ubits each. Catalyst’s advanced CMOS technology sub-
t4stantially reduces device power requirements. The
I Commercial, industrial, automotive and
extended automotive temperature ranges
I Write protection
– Entire array protected when WP at V
IH
I 1,000,000 Program/erase cycles
I 100 year data retention
CAT24WC32/64 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
ePIN CONFIGURATION
DIP Package (P, L, GL)
heA0
A1
SA2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
ataSOIC Package (J, W, K, X, GW, GX)
.DA0
A1
A2
wVSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
256
E2PROM
XDEC 128/256 128/256 X 256
CONTROL
WP LOGIC
wPIN FUNCTIONS
w omPin Name
Function
.cA0, A1, A2 Device Address Inputs
t4USDA
Serial Data/Address
eSCL Serial Clock
heWP Write Protect
SCL STATE COUNTERS
SVCC +1.8V to +5.5V Power Supply
ataVSS Ground
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
.D* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WC32/64 F02
ww© 2005 by Catalyst Semiconductor, Inc.
wCharacteristics subject to change without notice
1
Doc. No. 1039, Rev. G






CAT24WC32 Datasheet, Funktion
CAT24WC32/64
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC32/64. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC32/64 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC32/64 writes up to 32/64 bytes of data, in
a single write cycle, using the Page Write operation.
CAT24WC32/64, Die revision B = 32 byte page.
CAT24WC64, Die revision D = 64 byste page. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31/63 additional bytes. After each byte has
been transmitted, CAT24WC32/64 will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain un-
changed.
Figure 6. Byte Write Timing
If the Master transmits more than 32/64 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
When all 32/64 bytes are received, and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received
data is written to the CAT24WC32/64 in a single
write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC32/64 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC32/64 is still busy with the
write operation, no ACK will be returned. If
CAT24WC32/64 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC32/64
S
T
BUS ACTIVITY: A SLAVE
MASTER R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
DATA
S
T
O
P
SDA LINE S
X XX *
P
A A AA
C C CC
K K KK
24WC32/64 F08
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
X XX *
A
C
K
A
C
K
* = Don't care bit for 24WC32
X= Don't care bit
A
C
K
DATA
DATA n
DATA n+31/63
S
T
O
P
P
A AA A
C CC C
K KK K
24WC32/64 F09
Doc. No. 1039, Rev. G
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT24WC32 pdf, datenblatt
REVISION HISTORY
Date
7/7/2004
7/28/2004
Rev.
E
F
Reason
Added die revision to Ordering Information
Updated Features
Updated DC operating characteristics and notes
08/17/2005
G
Edit Features
Edit Pin Functions
Edit Reliability Characteristics
Edit D.C. Operating Characteristics
Edit A.C. Characteristics
Add Package Dimensions
Edit Ordering Information
Copyrights, Trademarks and Patents
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #: 1039
Revison:
G
Issue date: 08/17/05

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