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PDF CAT24WC17 Data sheet ( Hoja de datos )
| Número de pieza | CAT24WC17 | |
| Descripción | 2K/4K/8K/16K-Bit Serial E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT24WC17 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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Preliminary
CAT24WC03/05/09/17
2K/4K/8K/16K-Bit Serial E2PROM
FEATURES
s 400 KHZ I2C Bus Compatible*
s 1.8 to 6.0Volt Operation
s Low Power CMOS Technology
s Write Protect Feature
–Top 1/2 Array Protected When WP at VIH
s 16-Byte Page Write Buffer
DESCRIPTION
The CAT24WC03/05/09/17 is a 2K/4K/8K/16K-bit Serial
CMOS E2PROM internally organized as 256/512/1024/
2048 words of 8 bits each. Catalyst’s advanced CMOS
technology substantially reduces device power require-
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
s Self-Timed Write Cycle with Auto-Clear
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package
s Commercial, Industrial and Automotive
Temperature Ranges
ments. The CAT24WC03/05/09/17 features a 16-byte
page write buffer. The device operates via the I2C bus
serial interface, has a special write protection feature,
and is available in 8-pin DIP or 8-pin SOIC
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
A0
A1
A2
VSS
TSSOP Package (U)
(** Available for 24WC03 only)
18
27
SS
36
45
VCC
WP
SCL
SDA
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WCXX F03
Doc. No. 25063-00 2/98 S-1
1 page  
Preliminary
CAT24WC03/05/09/17
for 24WC03. If only one 24WC03 is addressed on the
bus, all three address pins (A0, A1, and A2) can be left
floating or connected to VSS
A total of four devices can be addressed on a single bus
when using 24WC05 device. Only A1 and A2 address
pins are used with this device. The A0 address pin is a
no connect pin and can be tied to VSS or left floating. If
only one 24WC05 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or con-
nected to VSS.
Only two devices can be cascaded when using 24WC09.
The only address pin used with this device is A2. The A0
and A1address pins are no connect pins and can be tied
to VSS or left floating. If only one 24WC09 is being
addressed on the bus, the address pin (A2) can be left
floating or connected to VSS.
The 24WC17 is a stand alone device. In this case, all
address pins (A0, A1and A2) are no connect pins and
can be tied to VSS or left floating.
WP: Write Protect
If the WP pin is tied to VCC the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05/09/17
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
24WC03 1 0 1 0 A2 A1 A0 R/W
24WC05 1 0 1 0 A2 A1 a8 R/W
24WC09 1 0 1 0 A2 a9 a8 R/W
24WC17 1 0 1 0 a10 a9 a8 R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
5020 FHD F06
5 Doc. No. 25063-00 2/98 S-1
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CAT24WC17.PDF ] | |
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