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DG444 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DG444
Beschreibung Improved / Quad / SPST Analog Switches
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 8 Seiten
DG444 Datasheet, Funktion
19-4705; Rev 1; 4/94
Improved, Quad, SPST Analog Switches
_______________General Description
Maxim’s redesigned DG444/DG445 analog switches
now feature on-resistance matching (4max) between
switches and guaranteed on-resistance flatness over
the signal range (9max). These low on-resistance
switches conduct equally well in either direction. They
guarantee low charge injection (10pC max), low power
consumption (35µW max), and an ESD tolerance of
2000V minimum per Method 3015.7. The new design
offers lower off leakage current over temperature (less
than 5nA at +85°C).
The DG444/DG445 are quad, single-pole/single-throw
(SPST) analog switches. The DG444 has 4 normally
closed switches and the DG445 has 4 normally open
switches. Switching times are less than 250ns for tON
and less than 70ns for tOFF. Operation is from a single
+10V to +30V supply, or bipolar ±4.5V to ±20V sup-
plies. Maxim’s improved DG444/DG445 continue to be
fabricated with a 44V silicon-gate process.
________________________Applications
Sample-and-Hold Circuits
Communication Systems
Test Equipment
Battery-Operated Systems
Heads-Up Displays
PBX, PABX
Guidance and Control Systems Audio Signal Routing
Military Radios
Modems/Faxes
______________________New Features
o Plug-In Upgrades for Industry-Standard DG444/DG445
o Improved rON Match Between Channels (4max)
o Guaranteed rFLAT(ON) Over Signal Range (9max)
o Improved Charge Injection (10pC max)
o Improved Off Leakage Current Over Temperature
(<5nA at +85°C)
o Withstand Electrostatic Discharge (2000V min)
per Method 3015.7
__________________Existing Features
o Low rDS(ON) (85max)
o Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20V
o Low Power Consumption (35µW max)
o Rail-to-Rail Signal Handling
o TTL/CMOS-Logic Compatible
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
DG444CJ
0°C to +70°C
16 Plastic DIP
DG444DY
0°C to +70°C
16 Narrow SO
DG444C/D
0°C to +70°C
Dice*
DG444DJ
-40°C to +85°C
16 Plastic DIP
DG444DY
-40°C to +85°C
16 Narrow SO
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
_____________________Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
DG444
16 IN2
15 D2
14 S2
13 V+
12 VL
11 S3
10 D3
9 IN3
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
DG445
16 IN2
15 D2
14 S2
13 V+
12 VL
11 S3
10 D3
9 IN3
DIP/SO
DG444
LOGIC
SWITCH
0 ON
1 OFF
DIP/SO
DG445
LOGIC
SWITCH
0 OFF
1 ON
SWITCHES SHOWN FOR LOGIC "0" INPUT
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.






DG444 Datasheet, Funktion
Improved, Quad, SPST Analog Switches
_____________________Pin Description
PIN
1, 16, 9, 8
2, 15, 10, 7
3, 14, 11, 6
4
5
12
13
NAME
IN1-IN4
D1-D4
S1-S4
V-
GND
VL
V+
FUNCTION
Logic Control Inputs
Drain Outputs
Source Outputs
Negative Supply-Voltage Input
Ground
Logic Supply-Voltage Input
Positive Supply-Voltage Input—
connected to substrate
__________Applications Information
General Operation
1. Switches are open when power is off.
2. IN, D, and S should not exceed V+ or V-, even with
the power off.
3. Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other Than ±15V
Using supply voltages other than ±15V will reduce the
analog signal range. The DG444/DG445 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. VL
must be connected to +5V to be TTL compatible, or to
V+ for CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
VL , V-, and logic inputs. If power-supply sequenc-
ing is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
S
Vg
D
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
______________________________________________Timing Diagrams/Test Circuits
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT
0V
tf < 20ns
50% tr < 20ns
VOUT
0.8 x VOUT
tOFF
0.8 x VOUT
tON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
SWITCH
INPUT
LOGIC
INPUT
+3V
+5V
VL
D
IN
GND
+15V
V+
S
V-
DG444
DG445
RL
VOUT
CL
-15V
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( )VOUT = VD
RL
RL + rDS(ON)
6 _______________________________________________________________________________________

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