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CAT24WC129 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24WC129
Beschreibung 128K-Bit I2C Serial CMOS E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 8 Seiten
CAT24WC129 Datasheet, Funktion
Preliminary
CAT24WC129
128K-Bit I2C Serial CMOS E2PROM
FEATURES
s 1MHz I2C Bus Compatible*
s 1.8 to 6 Volt Operation
s Low Power CMOS Technology
s 64-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC129 is a 128K-bit Serial CMOS E2PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
s Write Protect Feature
– Top 1/4 Array Protected When WP at VIH
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP or 8-Pin SOIC
CAT24WC129 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J,K)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
24WC129 F01
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
XDEC 256
E2PROM
256X512
CONTROL
WP LOGIC
SCL STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC129 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25065-00 6/99 S-1






CAT24WC129 Datasheet, Funktion
CAT24WC129
Preliminary
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC129 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC129 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC129 is still busy with the
write operation, no ACK will be returned. If
CAT24WC129 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the top 1/4 array of memory
(locations 3000H to 3FFFH) is protected and becomes
read only. The CAT24WC129 will accept both slave and
byte addresses, but the memory location accessed is
protected from programming by the device’s failure to
send an acknowledge after the first byte of data is
received.
READ OPERATIONS
The READ operation for the CAT24WC129 is initiated in
the same manner as the write operation with one excep-
tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT24WC129’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E=16383),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24WC129
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
Figure 6. Byte Write Timing
S
T
BUS ACTIVITY: A SLAVE
MASTER R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
DATA
S
T
O
P
SDA LINE S
*=Don't Care Bit
**
A
C
K
A
C
K
P
AA
CC
KK
24WC129 F08
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
*=Don't Care Bit
BYTE ADDRESS
A15–A8
A7–A0
**
A
C
K
A
C
K
A
C
K
DATA
DATA n
DATA n+63
S
T
O
P
P
A AA A
C CC C
K KK K
24WC129 F09
Doc. No. 25065-00 6/99 S-1
6

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