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PDF EL7563 Data sheet ( Hoja de datos )
| Número de pieza | EL7563 | |
| Descripción | Monolithic 4 Amp DC/DC Step-Down Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EL7563 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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NOT RECO® MMESNEDDEEaDtEaLFS7O5hR5e4eNtEW DESIGNS
May 13, 2005
EL7563
FN7296.2
Monolithic 4 Amp DC/DC Step-Down
Regulator
The EL7563 is an integrated, full-featured synchronous step-
down regulator with output voltage adjustable from 1.0V to
2.5V. It is capable of delivering 4A continuous current at up
to 95% efficiency. The EL7563 operates at a constant
frequency pulse width modulation (PWM) mode, making
external synchronization possible. Patented on-chip
resistorless current sensing enables current mode control,
which provides cycle-by-cycle current limiting, over-current
protection, and excellent step load response. The EL7563
features power tracking, which makes the start-up
sequencing of multiple converters possible. A junction
temperature indicator conveniently monitors the silicon die
temperature, saving the designer time on the tedious
thermal characterization. The minimal external components
and full functionality make this EL7563 ideal for desktop and
portable applications.
The EL7563 is offered in 20-pin SO and 28-pin HTSSOP
packages.
Pinout
EL7563
(20-PIN SO)
TOP VIEW
R4
22Ω C3
0.22µF
C1
VIN 330µF
3.3V
C5
1 VREF
0.1µF
2 SGND
C4
3 COSC
390pF
4 VDD
C2
5 VTJ
2.2nF
6 PGND
EN 20
FB 19
PG 18
VDRV 17
VHI 16
LX 15
7 PGND LX 14
8 VIN PGND 13
9 STP PGND 12
10 STN PGND 11
D2 D4
C8
D3
D1
0.22µF
C6
0.22µF
C9
0.1µF
L1
4.7µH
C10
2.2nF
VOUT
2.5V
4A
R2
1.58kΩ
C7
330µF
R1
1kΩ
Features
• Integrated synchronous MOSFETs and current mode
controller
• 4A continuous output current
• Up to 95% efficiency
• Internal patented current sense
• Cycle-by-cycle current limit
• 3V to 3.6V input voltage
• Adjustable output voltage 1V to 2.5V
• Precision reference
• ±0.5% load and line regulation
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• Internal soft-start
• Over-voltage protection
• Junction temperature indicator
• Over-temperature protection
• Under-voltage lockout
• Multiple supply start-up tracking
• Power-good indicator
• 20-pin SO (0.300”) package
• 28-pin HTSSOP package
• Pb-Free available (RoHS compliant)
Applications
• DSP, CPU core, and I/O supplies
• Logic/Bus supplies
• Portable equipment
• DC/DC converter modules
• GTL + Bus power supply
Typical Application Diagrams continued on page 3
Manufactured Under U.S. Patent No. 5,7323,974
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
EL7563
Pin Descriptions
20-PIN SO
(0.300”)
28-PIN
HTSSOP
PIN NAME
PIN FUNCTION
1 1 VREF Bandgap reference bypass capacitor; typically 0.1µF to SGND
2 2 SGND Control circuit negative supply or signal ground
3 3 COSC Oscillator timing capacitor (see performance curves)
4
4
VDD
Control circuit positive supply; normally connected to VIN through an RC filter
5 5 VTJ Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
6, 7
6, 7, 8, 9
PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
8
10, 11
VIN Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
9 13 STP Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2µA internal pull down current
10
14
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2µA internal pull up current
11, 12, 13
15, 16
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
14, 15
18, 19, 20, 21,
22, 23
LX Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
16 24 VHI Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF
capacitor
17 25 VDRV Positive supply of low-side driver and input voltage for high side boot strap
18 26 PG Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
19 27 FB Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
20 28 EN Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves (20 Pin SO Package)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
VIN=3.3V
100
95
90
VO=2.5V
VO=1.8V
85
80 VO=1.2V
75 VO=1V
70
0 0.5 1 1.5 2 2.5 3 3.5 4
LOAD CURRENT IO (A)
FIGURE 1. EL7563CM EFFICIENCY vs IO
VIN=3.3V
100
95 VO=2.5V
90
85
80 VO=1.8V
75 VO=1.2V
70
65
60
0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6
IO (A)
FIGURE 2. EL7563CRE EFFICIENCY
4
5 FN7296.2
May 13, 2005
5 Page 
EL7563
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7563. The external VREF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1µF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external source. If the oscillator is
driven by an external source care must be taken in selecting
the ramp amplitude. Since CSLOPE value is derived from the
COSC ramp, changes to COSC ramp will change the
CSLOPE compensation ramp which determine the open-loop
gain of the system.
When external synchronization is required, always choose
COSC such that the free-running frequency is at least 20%
lower than that of sync source to accommodate component
and temperature variations. Figure 22 shows a typical
connection.
EXTERNAL
OSCILLATOR
100pF BAT54S
390pF
1
2
3
5
6
7
8
9
10
EL7563
FIGURE 22. OSCILLATOR SYNCHRONIZATION
20
19
18
16
15
14
13
12
11
Junction Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the system is in fault state and will be shut
down. The upper and low trip-points are set to 135°C and
115°C respectively.
The VTJ pin is an accurate indication of the internal silicon
junction temperature (see performance curve.) The junction
temperature TJ (°C) can be deducted from the following
relation:
TJ
=
75 + 1----.--2----–-----V----T----J--
0.00384
Where VTJ is the voltage at VTJ pin in volts.
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches a value of approximately 2.9V. About 300mV
hysteresis is present to eliminate noise-induced
oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic high on the PG output indicates that the regulated
output voltage is within about +10% of the nominal selected
output voltage.
11 FN7296.2
May 13, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet EL7563.PDF ] | |
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